Abstract: The present disclosure relates to a stacked SPAD image sensor with a CMOS Chip and an imaging chip bonded together, to improve the fill factor of the SPAD image sensor, and an associated method of formation. In some embodiments, the imaging chip has a plurality of SPAD cells disposed within a second substrate. The CMOS Chip has a first interconnect structure disposed over a first substrate. The imaging chip has a second interconnect structure disposed between the second substrate and the first interconnect structure. The CMOS Chip and the imaging chip are bonded together through along an interface disposed between the first interconnect structure and the second interconnect structure.

Abstract: A technique includes forming a film containing a first element, a second element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing supplying a first precursor having chemical bonds between the first elements to a substrate, supplying a second precursor having chemical bonds between the first element and carbon without having the chemical bonds between the first elements to the substrate, and supplying a first reactant containing the second element to the substrate.

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.

Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

Abstract: Provided is protective film-forming sheet (2) including: a protective film-forming film (1) having a light transmittance at a wavelength of 1064 nm of 55% or greater and a light transmittance at a wavelength of 550 nm of 20% or less; and a release sheet (21) which is laminated on one or both faces of the protective film-forming film (1). According to this protective film-forming sheet (2), it is possible to form a protective film which allows a workpiece such as a semiconductor wafer to have a modified layer disposed in advance therein by a laser so that the workpiece can be split through the application of force thereon, while preventing grinding marks on the workpiece or a product formed therefrom from being visible to the naked eye.

Abstract: A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

Abstract: An integrated circuit includes a substrate member having a surface region and a CMOS IC layer overlying the surface region. The CMOS IC layer has at least one CMOS device. The integrated circuit also includes a bottom isolation layer overlying the CMOS IC layer, a shielding layer overlying a portion of the bottom isolation layer, and a top isolation layer overlying a portion of the bottom isolation layer. The bottom isolation layer includes an isolation region between the top isolation layer and the shielding layer. The integrated circuit also has a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer. The MEMS layer includes at least one MEMS structure having at least one movable structure and at least one anchored structure. The at least one anchored structure is coupled to a portion of the top isolation layer, and the at least one movable structure overlies the shielding layer.

Abstract: A method for manufacturing solar cell includes the following. A solution containing aluminum elements is misted. The misted solution is sprayed onto the main surface of a p-type silicon substrate in the atmosphere, to thereby form an aluminum oxide film. Then, a solar cell is produced using the p-type silicon substrate including the aluminum oxide film formed thereon.

Abstract: An image sensor array including a carrier substrate; a first group of photodiodes coupled to the carrier substrate, where the first group of photodiodes include a first photodiode, and where the first photodiode includes a semiconductor layer configured to absorb photons at visible wavelengths and to generate photo-carriers from the absorbed photons; and a second group of photodiodes coupled to the carrier substrate, where the second group of photodiodes include a second photodiode, and where the second photodiode includes a germanium-silicon region fabricated on the semiconductor layer, the germanium-silicon region configured to absorb photons at infrared or near-infrared wavelengths and to generate photo-carriers from the absorbed photons.

Abstract: An organic electroluminescence display device includes a substrate; a thin film transistor that is formed on the substrate; a light emitting region that has a lower electrode, a light emitting layer, and an upper electrode formed for each of a plurality of pixels arranged in a matrix shape on the thin film transistor; and a contact hole that is formed on the outside of the light emitting region in one corner portion of the pixel and connects the thin film transistor and the lower electrode for each pixel in a plan view. Only one pair of pixels of four pixels that share an intersection point of boundaries of the pixels arranged in the matrix shape, which are arranged in a diagonal manner have the contact holes at the corner portions having the intersection point.

Abstract: An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W.

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate.

Abstract: A display device includes a first base substrate, a second base substrate, pixels, a first polarizer, and a second polarizer. The first base substrate includes light transmitting areas and a light blocking area surrounding each of the light transmitting areas. The pixels respectively overlap the light transmitting areas. The first and second polarizers are spaced apart from each other such that the pixels are disposed therebetween. At least one of the first and second polarizers includes a plurality of optical conversion layers, each of which comprises a plurality of lattice wires.

Abstract: A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.

Abstract: A method of manufacturing a silicon carbide semiconductor device, having a silicon carbide semiconductor element substrate and a surface electrode film forming an ohmic contact between them. A first electrode film including nickel is formed on the substrate surface. A second electrode film with nickel silicide is formed on a first electrode film surface. The surface film is formed having the ohmic contact between the substrate surface and the first electrode film by annealing to cause silicon of the substrate and nickel of the first electrode film to react and convert the first electrode film to silicide. The first electrode film is formed with a thickness so that during annealing, an amount of carbon atoms is liberated from the substrate and diffuses toward the first electrode film, wherein the liberated amount is equal to or less than the amount of carbon atoms that the second electrode film is able to take in during annealing.

Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.

Abstract: The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.

Abstract: Provided are an organic light emitting display (OLED) apparatus and a manufacturing method thereof. The OLED apparatus includes: a thin film transistor (TFT) array substrate including: a support substrate, including a soft material and a plurality of TFTs on the support substrate corresponding to a plurality of pixel areas, a light emitting array (LEA) including a plurality of organic light emitting devices on the TFT array substrate corresponding to the plurality of pixel areas, a sealing structure facing the TFT array substrate, the LEA interposed between the TFT array substrate and the sealing structure, and an adhesive layer between the LEA and the sealing structure to adhere the LEA to the sealing structure, wherein the sealing structure includes: a protective layer on the LEA, a sealing layer over the TFT array substrate, and a barrier layer adhering the protective layer to the sealing layer.