Abstract: One embodiment provides a semiconductor device comprising: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer disposed on the second semiconductor layer; and a reflective layer disposed on the third semiconductor layer, wherein the part between the first and second semiconductor layers, the part between the third and second semiconductor layers, and the second semiconductor layer comprise a depletion region, and the conductivity of the first semiconductor layer and the conductivity of the third semiconductor layer are different from each other, and the second semiconductor layer comprises an intrinsic semiconductor layer.

Abstract: A device for direct liquid cooling is disclosed. The device includes a packaged assembly disposed on a substrate. The device also includes a metal channel layer having a plurality of channels disposed on top of the packaged assembly, and a top seal disposed on the metal channel layer. The top seal has at least one inlet and at least one outlet for direct liquid cooling. The metal channel layer includes copper or silver. The packaged assembly can also include silicon channels. In addition, the method of producing the device is also disclosed.

Abstract: Disclosed is a manufacturing method of a complementary metal oxide semiconductor transistor, comprising a step of implementing a channel doping to an N-type channel region. The step comprises: preparing a low temperature polysilicon layer on a substrate, and patterning the low temperature polysilicon layer to form the N-type channel region correspondingly above a light shielding pattern; coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development; implementing the channel doping to the N-type channel region with shielding of the negative photoresist mask plate. Further disclosed is a manufacturing method of an array substrate, applied with the aforesaid manufacturing method of the complementary metal oxide semiconductor transistor.

Abstract: In an embodiment, a method for producing a plurality of optoelectronic semiconductor components is disclosed, wherein the method includes inserting a plurality of optoelectronic semiconductor chips with a suitable orientation into a linear feeding device, conveying the optoelectronic semiconductor chips to an injection device having an outlet opening, encapsulating the optoelectronic semiconductor chips with at least one cladding layer in the injection device and pressing the encapsulated optoelectronic semiconductor chips out of the outlet opening, wherein a compound of optoelectronic semiconductor chips is formed in which the optoelectronic semiconductor chips are connected to one another by the at least one cladding layer and separating the compound into a plurality of optoelectronic semiconductor components each component having an optoelectronic semiconductor chip which is at least partially encapsulated by the at least one cladding layer.

Abstract: A method for producing a semiconductor component is proposed. The method includes providing a housing. At least one semiconductor chip is arranged in a cavity of the housing. Furthermore, an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire. The method furthermore includes applying a protective material on the electrical contact of the semiconductor chip and also on a region of the bond wire which is adjacent to the electrical contact of the semiconductor chip, and/or on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing. Moreover, the method also includes filling at least one partial region of the cavity with a gel.

Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: A light emitting device includes a substrate including a base member including a front surface, a rear surface opposite to the front surface, a bottom surface perpendicular to the front surface, and a top surface opposite to the bottom surface, a first wiring portion located on the front surface, and a second wiring portion located on the rear surface; a light emitting element electrically connected with the first wiring portion; and a first reflective member covering a lateral surface of the light emitting element and the front surface of the base member. The base member has a recessed portion opened on the rear surface and the bottom surface. The substrate includes a third wiring portion covering an inner wall of the recessed portion and electrically connected with the second wiring portion, and a via in contact with the first wiring portion, the second wiring portion and the third wiring portion.

Abstract: Embodiments are disclosed that improve etch uniformity during multi-patterning processes for the manufacture of microelectronic workpieces by reshaping spacers using thermal decomposition materials as a protective layer. Because the thermal decomposition material can be removed through thermal treatment processes without requiring etch processes, spacers can be reshaped with no spacer profile change or damage while suppressing undesired gouging differences in underlying layers and related degradation in etch uniformity.

Abstract: A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Abstract: A method for operating a multiple axis machine includes controlling drives of the machine with a machine control system and monitoring the machine with a fail-safe control system having first and second redundant channels. Each of the first and second channels receives first input target values and first input actual values from the machine control system, and compares first reference target values (based on the first input target values) with first reference actual values (based on the first input actual values). A fault reaction is triggered if there is a deviation between the compared values that exceeds a specified tolerance. The first input values comprise reference position values of a machine-fixed reference or time derivatives thereof, and the machine control system determines target and/or actual reference position values based on a transformation between reference position values of the machine-fixed reference and axial position values of the machine.

Abstract: The present disclosure provides an array substrate, a manufacturing method of an array substrate, and a display device. The array substrate includes: a base substrate; a first signal line, extending in a first direction and located on the base substrate; a second signal line, extending in a second direction and located on a side of the first signal line away from the base substrate and insulated with the first signal line, the first direction and the second direction crossing with each other. A side of the first signal line facing the second signal line is provided with a groove, the groove is located at a crossing region between the first signal line and the second signal line, in the crossing region, an otherographic projection of the second signal line on the base substrate completely falls into an orthographic projection of the groove on the base substrate.

Abstract: A manufacturing method for carbon nanotube composite film is disclosed. The method comprises steps of: providing a substrate; coating a first aqueous solution dissolved with a charged polymer on a substrate to form a polymer film; dispersing a single-wall carbon nanotube powder into a second aqueous solution dissolved with a charged compound in order to obtain a semiconductor-type single-wall carbon nanotube aqueous solution, and charge properties of the charged compound and the charged polymer are opposite; coating the semiconductor-type single-wall carbon nanotube aqueous solution on the polymer film; after standing for a predetermined period of time, washing with a deionized water to remove an unabsorbed semiconductor-type single-wall carbon nanotube and excess charged polymer; and air drying, forming a carbon nanotube film on the polymer film. A manufacturing method for carbon nanotube TFT and a carbon nanotube TFT are also disclosed. The carbon nanotubes can be well tiled onto the substrate.

Abstract: Provided are an array substrate and a manufacturing method thereof. A first wire of a fanout line of the array substrate is divided into a plurality of first sections. A second wire of the fanout line is divided into a plurality of second sections corresponding to the first sections. Each of the first sections is electrically connected to the second section corresponding thereof. Thus, as a certain position of the first wire or the second wire is broken, only a resistance of the first section or the second section where the broken position is located is changed, so that a blocking effect on the entire fanout lines is not large, thereby reducing or avoiding appearance of a light line.

Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, an underfill material with improved surface coverage is provided between adjacent pixels of a pixelated-LED chip. The underfill material may be arranged to cover all lateral surfaces between the adjacent pixels. In some aspects, discontinuous substrate portions are formed before application of underfill materials. In some aspects, a wetting layer is provided to improve wicking or flow of underfill materials during various fabrication steps.

Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, an underfill material with improved surface coverage is provided between adjacent pixels of a pixelated-LED chip. The underfill material may be arranged to cover all lateral surfaces between the adjacent pixels. In some aspects, discontinuous substrate portions are formed before application of underfill materials. In some aspects, a wetting layer is provided to improve wicking or flow of underfill materials during various fabrication steps.

Abstract: A pixel arrangement structure includes a plurality of pixel groups that are periodically arranged. Each pixel group includes four pixels, a first pixel and a second pixel are arranged in a same row, a third pixel and a fourth pixel are arranged in adjacent another row, the first pixel and the third pixel are arranged in a same column, and the second pixel and the fourth pixel are arranged in adjacent another column. An arrangement of sub-pixels in the first pixel is different from an arrangement of sub-pixels in the second pixel, an arrangement of sub-pixels in the third pixel is same as the arrangement of the sub-pixels in the second pixel, and an arrangement of sub-pixels in the fourth pixel is same as the arrangement of the sub-pixels in the first pixel. An organic light emitting device, a display device and a mask are also provided.

Abstract: A quantum light emitting device includes a carrier substrate, an insulator, a first semiconductor device, a second semiconductor device, a first contact, and a second contact. The quantum light device includes a carrier substrate comprising silicon and configured with an electrically insulating top surface. The quantum light device also includes an insulator configured on the carrier substrate. The quantum light device includes a first semiconductor structure comprising a first semiconductor material configured on the insulator. Further, the quantum light device includes a second semiconductor structure comprising a second semiconductor material configured on the insulator, with an overlap region of the second semiconductor structure electrically coupling with the first semiconductor structure, a dimensional characteristic of the overlap region being configured to limit a photon emission from the overlap region to a single photon.

Abstract: Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding.

Abstract: The present invention provides a process for fabricating an n-cell supercapacitor stack, including a step of providing at least n+1 identical, or substantially identical, electrically inert conductive sheets having a defined perimeter, n identical, or substantially identical, ion-permeable insulating sheets having a defined perimeter, n identical, or substantially identical, first electrodes having a defined perimeter, n identical, or substantially identical, second electrodes having a defined perimeter, and at least n matching dielectric frames having an outer perimeter, which is larger than the perimeter of the conductive sheet and the perimeter of the insulating sheet; a step of assembling the supercapacitor stack, a step of disposing an additional conductive sheet on top of the nth second electrode; and a step of attaching adjacent units onto one another, such that at least one of the frames within each unit is attached to at least one of the frames within each respective unit adjacent thereto.