Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, an underfill material with improved surface coverage is provided between adjacent pixels of a pixelated-LED chip. The underfill material may be arranged to cover all lateral surfaces between the adjacent pixels. In some aspects, discontinuous substrate portions are formed before application of underfill materials. In some aspects, a wetting layer is provided to improve wicking or flow of underfill materials during various fabrication steps.

Abstract: A pixel arrangement structure includes a plurality of pixel groups that are periodically arranged. Each pixel group includes four pixels, a first pixel and a second pixel are arranged in a same row, a third pixel and a fourth pixel are arranged in adjacent another row, the first pixel and the third pixel are arranged in a same column, and the second pixel and the fourth pixel are arranged in adjacent another column. An arrangement of sub-pixels in the first pixel is different from an arrangement of sub-pixels in the second pixel, an arrangement of sub-pixels in the third pixel is same as the arrangement of the sub-pixels in the second pixel, and an arrangement of sub-pixels in the fourth pixel is same as the arrangement of the sub-pixels in the first pixel. An organic light emitting device, a display device and a mask are also provided.

Abstract: A quantum light emitting device includes a carrier substrate, an insulator, a first semiconductor device, a second semiconductor device, a first contact, and a second contact. The quantum light device includes a carrier substrate comprising silicon and configured with an electrically insulating top surface. The quantum light device also includes an insulator configured on the carrier substrate. The quantum light device includes a first semiconductor structure comprising a first semiconductor material configured on the insulator. Further, the quantum light device includes a second semiconductor structure comprising a second semiconductor material configured on the insulator, with an overlap region of the second semiconductor structure electrically coupling with the first semiconductor structure, a dimensional characteristic of the overlap region being configured to limit a photon emission from the overlap region to a single photon.

Abstract: Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding.

Abstract: The present invention provides a process for fabricating an n-cell supercapacitor stack, including a step of providing at least n+1 identical, or substantially identical, electrically inert conductive sheets having a defined perimeter, n identical, or substantially identical, ion-permeable insulating sheets having a defined perimeter, n identical, or substantially identical, first electrodes having a defined perimeter, n identical, or substantially identical, second electrodes having a defined perimeter, and at least n matching dielectric frames having an outer perimeter, which is larger than the perimeter of the conductive sheet and the perimeter of the insulating sheet; a step of assembling the supercapacitor stack, a step of disposing an additional conductive sheet on top of the nth second electrode; and a step of attaching adjacent units onto one another, such that at least one of the frames within each unit is attached to at least one of the frames within each respective unit adjacent thereto.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.

Abstract: A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, and a plurality of bit lines. The semiconductor substrate includes a plurality of active areas. The word lines are disposed parallel to one another, and each of the word lines is elongated in a first direction. Each of the word lines overlaps at least one of the active areas. The bit lines are disposed parallel to one another, and each of the bit lines is elongated in a second direction. Each of the bit lines overlaps at least one of the active areas. The bit lines cross the word lines. An included angle between the first direction and the second direction is larger than 0 degree and smaller than 90 degrees.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

Abstract: A package structure is provided. The package structure includes a substrate, a plurality of active components, a plurality of separated metal parts and an encapsulation material. The substrate has a first surface and a second surface. Each active component has a first surface and a second surface. Each metal part has a first surface and a second surface. The first surface of each active component is connected to the first surface of the substrate. The first surface of one metal part is connected to the second surface of one active component. Each metal part extends to connect to the first surface of the substrate. The encapsulation material covers the first surface of the substrate and surrounds the active components and the metal parts. The second surface of each metal part and the second surface of the substrate are exposed from the encapsulation material.

Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

Abstract: Systems and methods for providing a phase modulator. The methods comprise creating a Field Effect Transistor (FET) by: placing a crystal structure displaying ambipolarity on a substrate comprising an oxide layer and a conductive silicon layer, the conductive silicon layer providing a gating electrical contact for the phase modulator, and forming source and drain electrical contacts on the crystal structure using e-beam lithography and an e-beam evaporator. The methods also comprising: annealing the FET to improve an interface between the crystal structure and the source and drain electrical contacts; and coating the FET with a dielectric layer to reduce or eliminate hysteresis so that a functionality of the phase modulator is improved.

Abstract: A stacked III-V semiconductor component having a p+ region with a top side, a bottom side, and a dopant concentration of 5·1018-5·1020 N/cm3, a first n? layer with a top side and a bottom side, a dopant concentration of 1012-1017 N/cm3, and a layer thickness of 10-300 ?m, an n+ region with a top side, a bottom side, and a dopant concentration of at least 1018 N/cm3, wherein the p+ regions, the n? layer, and the n+ region follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the n+ region or the p+ region is formed as the substrate layer, and the n? layer comprises chromium with a concentration of at least 1014 N/cm3 or at least 1015 N/cm3.

Abstract: A BEOL eFuse is provided that includes a fuse element-containing layer having an entirely planar topmost surface. An upper portion of the fuse element-containing layer including the entirely planar topmost surface is present above a topmost surface of a second interconnect dielectric material layer, and a lower portion of the fuse-element containing layer is present in an opening that is formed in the second interconnect dielectric material layer and has a surface that contacts a first electrode structure that is partially embedded in a first interconnect dielectric material layer which underlies the second interconnect dielectric material layer. A second electrode structure that is present in a third interconnect dielectric material layer that overlies the second interconnect dielectric material layer contacts a portion of the planar topmost surface of the fuse-element-containing layer.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.