Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.

Abstract: A conductive paste including: a conductive powder containing silver; an indium powder; a silver-tellurium-coated glass powder; a solvent; and an organic binder, wherein the silver-tellurium-coated glass powder is a silver-tellurium-coated glass powder including a tellurium-based glass powder containing tellurium in an amount of 20% by mass or more, and a coating layer on a surface of the tellurium-based glass powder, the coating layer containing silver and tellurium as a main component.

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Abstract: Provided is a laser annealing device provided with an irradiation unit in which a plurality of lens arrays each comprising one or more lenses are arranged at a first interval, wherein, while scanning a substrate having: a plurality of first area arrays each of which comprises one or more areas to be irradiated and which are arranged at the first interval; and a plurality of second area arrays which are arranged apart from the first area arrays toward one side in a direction orthogonal to the first area arrays by a second interval smaller than the first interval, the irradiation unit irradiates the areas to be irradiated with a laser beam through the one or more lenses. At least one type of area array, in one pixel unit row that comprises a plurality of area arrays including the first and second area arrays, is irradiated with a laser by use of a lens array different from the ones used for the other types of area arrays.

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Abstract: Aluminum oxide films with a thickness of between about 10-50 ?, characterized by a dielectric constant (k) of less than about 7 (such as about 4-6) and having a density of at least about 2.5 g/cm3 (such as about 3.0-3.2 g/cm3) are deposited on partially fabricated semiconductor devices over a metal (e.g., cobalt or copper) such that the metal does not show signs of oxidation. In some embodiments, the films are etch stop films.

Abstract: A method and system for analyzing waveform capture data is provided. In one aspect, the method comprises receiving, by a controller from an intelligent electronic device, waveform capture data indicative of an electrical event, extracting, from the waveform capture data, electrical event data, extracting, from memory associated with the controller, additional data, classifying the waveform capture data into a category of a plurality of categories using the electrical event data, comparing the electrical event data and the additional data to stored data, diagnosing the electrical event and a cause of the electrical event based on the comparison and providing an indication of the cause of the electrical event.

Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

Abstract: The invention relates to semiconductor devices for converting ionizing radiation into an electrical signal. The present ionizing radiation sensor has an n+-i-p+ structure, produced using the planar process. The sensor contains an i-region in the form of a high-resistivity substrate of high-purity float-zone silicon with p-type conductivity, having on its front face n+-regions (2, 3), an SiO2 layer (4), aluminium metallization (5), and a passivation layer. On the front face of the substrate (1) n-regions (2) are formed by ion implantation; a masking layer of SiO2 (layer 4) is grown; aluminium metallization (5) is deposited; and a passivation layer (6) is applied.

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

Abstract: Various methods and apparatuses are disclosed. A method may include disposing at least one die on a location on a carrier substrate, forming at least one stud bump on each of at least one die, forming a phosphor layer on the at least one stud bump and the at least one die, removing a top portion of the phosphor layer to expose the at least one stud bump, and removing a side portion of the phosphor layer located between two adjacent dies. An apparatus may include a die comprising top, bottom, and side surfaces. A phosphor layer may be disposed on the top, bottom, and side surfaces of the die. The phosphor layer may have substantially equal thicknesses on the top and side surfaces of the die as well as one or more stud bumps disposed on the top surface of the die.

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A first encapsulant is deposited over the first substrate and semiconductor die after forming the conductive pillar. A groove is formed in the first encapsulant around the conductive pillar. A first passive device is disposed over a second substrate. A second encapsulant is deposited over the first passive device and second substrate. The first substrate is mounted over the second substrate. A shielding layer is formed over the second encapsulant. A second passive device can be mounted over the second substrate opposite the first passive device and outside a footprint of the first substrate.

Abstract: Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.

Abstract: The present invention addresses the problem of enlarging a sensing area in an ultrasonic probe so as to achieve a higher definition. This ultrasonic diagnostic equipment is provided with an ultrasonic probe that comprises: a CMUT chip (2a) that has drive electrodes (3e)-(3j), etc., arranged in a grid-like configuration on a rectangular CMUT element section (21); and a CMUT chip (2b) that has drive electrodes (3p)-(3u), etc., arranged in a grid-like configuration on the rectangular CMUT element section (21), that is adjacent to the CMUT chip (2a), and in which the drive electrodes (3e)-(3j) of the adjacent CMUT chip (2a) are electrically connected to the respective drive electrodes (3p)-(3u) via bonding wires (4f)-(4i), etc.

Abstract: The present disclosure provides a manufacturing method of a thin film transistor, including: selecting a substrate, and forming a bottom gate, a gate insulating layer and a source-drain above the selected substrate, wherein the bottom gate and the source-drain adopts a conductive metal oxide with an adjustable work function as a metal conducting electrode; rinsing and drying the source-drain of the selected substrate, and ozone cleaning dried source-drain for a predetermined time under a predetermined illumination condition, bombarding the source-drain with oxygen plasma for a period of time, forming an active layer made of a carbon material over the source-drain; forming a passivation layer over the active layer. The implementation of the disclosure can reduce the contact resistance and improve the performance of the carbon-based thin film transistor device by adjusting the work function of the contact surface between the conductive metal and the active layer.

Abstract: The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.