Abstract: The present disclosure relates to a display panel. The display panel may include a substrate. The substrate may include a display area, a dummy area inside the display area, and a boundary area between the dummy area and the display area on the substrate. The display substrate may further include an isolation protrusion on the substrate at the boundary area. The isolation protrusion may be configured to isolate a functional layer in the display area from the functional layer in the dummy area, and at least a side surface of the isolation protrusion facing the dummy area may be covered by an isolation inorganic layer.

Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber; a substrate holder having a holding wall capable holding an outer periphery of the substrate; a process gas supply part provided above the reaction chamber, the process gas supply part having a first region supplying a first process gas and a second region around the first region supplying a second process gas having a carbon/silicon atomic ratio higher than that of the first process gas, an inner peripheral diameter of the second region being 75% or more and 130% or less of a diameter of the holding wall; a sidewall provided between the process gas supply part and the substrate holder, an inner peripheral diameter of the sidewall being 110% or more and 200% or less of an outer peripheral diameter of the second region; a first heater; a second heater; and a rotation driver.

Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.

Abstract: A method includes preparing a wafer including a substrate and a semiconductor structure, and irradiating an inner portion of the substrate at a predetermined depth in a thickness direction a plurality of times with laser pulses at a first time interval and a predetermined distance interval between irradiations. Each irradiation performed at the first time intervals in the step of irradiating the substrate with laser pulses includes irradiating the substrate at a first focal position in the thickness direction with a first laser pulse having a first pulse-energy; and after irradiating with the first laser pulse, irradiating the substrate with a second laser pulse performed after a second time interval, the second time interval being shorter than the first time interval and being in a range of 3 ps to 900 ps, and the second laser pulse having a second pulse-energy 0.5 to 1.5 times the first pulse-energy.

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.

Abstract: A pixel arrangement structure, an organic electroluminescent display panel, a metal mask, a display device are provided, the pixel arrangement structure including: first sub-pixels, second sub-pixels and third sub-pixels, all being not overlapped but being spaced apart; one first sub-pixels functions as a central point and other four first sub-pixels function as four vertices to define a first virtual rectangle comprising four second virtual rectangles in a 2×2 matrix in mirror symmetry; the second sub-pixels are at central points of side edges of the first virtual rectangle; two second sub-pixels at central positions of two adjacent side edges of the first virtual rectangle, one first sub-pixel at a vertice of the first virtual rectangle where the two adjacent side edges intersect, and another first sub-pixels at the central point of the first virtual rectangle define four vertices of each second virtual rectangle; the third sub-pixels are within the second virtual rectangles and each is shaped as: a concave

Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.

Abstract: A thermionic energy conversion system, preferably including one or more electron collectors, interfacial layers, encapsulation, and/or electron emitters. A method for manufacturing the thermionic energy conversion system. A method of operation for a thermionic energy conversion system, preferably including receiving power, emitting electrons, and receiving the emitted electrons, and optionally including convectively transferring heat.

Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel, where at least one of the plurality of transistors includes a second single crystal channel, where the second single crystal channel is disposed above the first single crystal channel, where at least one of the plurality of transistors includes a third single crystal channel, where the third single crystal channel is disposed above the second single crystal channel, where at least one of the plurality of transistors includes a fourth single crystal channel, and where the fourth single crystal channel is disposed above the third single crystal channel; and at least one region of oxide to oxide bonds.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a memory array region including a plurality of word lines formed linearly along a plane having a height (h1), a plurality of linear bit lines formed linearly along a plane having a height (h2) in a direction intersecting the plurality of word lines, and a plurality of memory cells provided between an intersection portion of each of the plurality of word lines with the plurality of bit lines and each of the plurality of bit lines, and a peripheral circuit region including a plurality of linear electrodes formed linearly along a plane having a height (h1), a plurality of linear electrodes formed linearly along a plane having the height (h2) in a direction intersecting the plurality of linear electrodes, and an insulators provided at least between the plurality of linear electrodes and the plurality of linear electrodes.

Abstract: An organic electroluminescent device includes a substrate, a number of first electrodes disposed on the substrate, each of the first electrodes used to form a light-emitting unit; an insulative layer disposed on the substrate and used to define a pixel region of the light-emitting unit; a number of second electrodes disposed on the substrate, each of the second electrodes used to form a light-emitting unit, wherein the second electrodes are spaced apart from one another to form a number of isolation grooves each between two adjacent second electrodes.

Abstract: According to an embodiment, a wafer (W) includes a layer (EL) to be etched, an organic film (OL), an antireflection film (AL), and a mask (MK1), and a method (MT) according to an embodiment includes a step of performing an etching process on the antireflection film (AL) by using the mask (MK1) with plasma generated in a processing container (12), in the processing container (12) of a plasma processing apparatus (10) in which the wafer (W) is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film (SX) on the surface of the mask (MK1), and steps ST6a to ST7 of etching the antireflection film (AL) by removing the antireflection film (AL) for each atomic layer by using the mask (MK1) on which the protective film (SX) is formed.

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

Abstract: Disclosed is a manufacturing method of a rigid organic light-emitting diode (OLED) display panel and a display panel. The method comprises steps of providing a first substrate having a first glass substrate and a flexible film; coating an organic compound on the first glass substrate; providing a second substrate; packaging the display area; and cutting and stripping a part of the first glass substrate at the non-display area of the packaged display panel, thereby improving the screen accounting of the display area in the rigid OLED display panel.

Abstract: A resin composition contains a 2-methylene-1,3-dicarbonyl compound and an initiator. The 2-methylene-1,3-dicarbonyl compound has a molecular weight of 180 to 10,000, and the initiator contains a basic substance having a pKa of 8 or greater.

Abstract: A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and first alignment marks; forming memory control circuits including first single crystal transistors, where the first single crystal transistors include portions of the single crystal layer; forming at least one second level above the first level; performing a first etch step including etching lithography windows within the at least one second level; performing a first lithographic step over the at least one second level aligned to the first alignment marks; and performing additional processing steps to form a plurality of first memory cells within the at last one second level, where each of the plurality of first memory cells include one of a plurality of second transistors, and where the plurality of second transistors are aligned to the first alignment marks with a less than 40 nm alignment error.

Abstract: Embodiments disclosed herein include methods of forming high quality silicon nitride films. In an embodiment, a method of depositing a film on a substrate may comprise forming a silicon nitride film over a surface of the substrate in a first processing volume with a deposition process, and treating the silicon nitride film in a second processing volume, wherein treating the silicon nitride film comprises exposing the film to a plasma induced by a modular high-frequency plasma source. In an embodiment, a sheath potential of the plasma is less than 100 V, and a power density of the high-frequency plasma source is approximately 5 W/cm2 or greater, approximately 10 W/cm2 or greater, or approximately 20 W/cm2 or greater.

Abstract: A circuit board assembly includes a circuit board, an electronic surface mount device (SMD), and a spacer that attaches the SMD to the circuit board. A coefficient of thermal expansion (CTE) of the spacer is closer to a CTE of the SMD than a CTE of the circuit board. The circuit board assembly also includes a flexible electrical lead that extends between and that is electrically connected to the SMD and the electrical node of the circuit board. Methods of manufacturing the circuit board assembly include selectively heating joining material at a predetermined heating rate and selectively cooling the joining material at a predetermined cooling rate to attach the flexible electrical leads to the SMD and the circuit board.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.