Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; a silicon nitride trench-fill layer disposed in the trench; an interlayer dielectric layer disposed on the silicon nitride trench-fill layer; a working gate striding over the fin structure, on the first side of the trench; a dummy gate striding over the fin structure, on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region.

Abstract: An improved method and system for analyzing multistate fluids using NIR spectroscopy. If the sample to be tested resides in a single state condition, the configuration file used in spectroscopic analysis will only be applied against a single model. However, if the sample to be tested is in a multi-state environment, an algorithm determines which model set of a plurality of model sets should be utilized based on the sample characteristics, and the configuration file used in spectroscopic analysis will be applied against the selected model. Results are generated showing the designated parameters.

Abstract: Provided is a display apparatus capable of reducing generation of defects during manufacturing of the display apparatus or while in use after being manufactured. The display apparatus includes a substrate including a bending area between a first area and a second area, the substrate being bent in the bending area about a bending axis; an inorganic insulating layer over the substrate and including a first feature that is either a first opening or a first groove, the first feature positioned to correspond to the bending area; and an organic material layer at least partially filling the first feature, and including a second feature that is a second opening or a second groove, the second feature extending along an edge of the substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.

Abstract: A grinding method, an OGS substrate and a manufacturing method of an OGS mother substrate are provided. The grinding method is used to grind the OGS substrate comprising a base substrate, wherein a shielding pattern is formed inside a periphery region of the base substrate, a reference mark is formed above the shielding pattern, the grinding method comprises: grinding an edge of the base substrate to form a chamfer; identifying edges of the reference mark and the base substrate; calculating a position distance between an outer edge of the reference mark and the edge of the base substrate corresponding thereto based on the identified edges of the reference mark and the base substrate; judging whether the position distance is smaller than a first distance; if it is judged that the position distance is smaller than the first distance, stopping grinding; otherwise, continuing to grind.

Abstract: An OGS substrate and a grinding method thereof are provided. The OGS substrate includes a base substrate, wherein a shielding pattern is formed inside a periphery region of the base substrate, a reference mark is formed above the shielding pattern, the grinding method comprises: grinding an edge of the base substrate to form a chamfer; identifying edges of the reference mark and the base substrate; calculating a position distance between an outer edge of the reference mark and the edge of the base substrate corresponding thereto based on the identified edges of the reference mark and the base substrate; judging whether the position distance is smaller than a first distance; if it is judged that the position distance is smaller than the first distance, stopping grinding; otherwise, continuing to grind.

Abstract: A game system includes a plurality of pedometers. The plurality of step count data respectively counted by the plurality of pedometers are acquired in the game apparatus. In the game apparatus, by utilizing the plurality of step count data, a predetermined arithmetic operation is executed, and the result of the arithmetic operation is reflected on the game. Alternatively, in a server, a predetermined arithmetic operation is executed by utilizing the plurality of step count data, and the result of the arithmetic operation is reflected on the game in the game apparatus. For example, game processing depending on the number of players walking in the same time slot is executed, or game processing according to the totalized value of the accumulated total step count values of the plurality of pedometers is executed.

Abstract: Structure and method for a backside capacitor using through-substrate vias (TSVs) and backside metal plates. The structure includes: a substrate, a device layer over the substrate, a first plurality of metal layers connected to the device layer, where the device layer and the first plurality of metal layers are disposed on a first side of the substrate, and a second plurality of metal layers disposed on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor and where a plurality of through-substrate vias (TSVs) extend between the first plurality of metal layers and the second plurality of metal layers.

Abstract: A light emitting device includes a substrate including a base member including a front surface, a rear surface opposite to the front surface, a bottom surface perpendicular to the front surface, and a top surface opposite to the bottom surface, a first wiring portion located on the front surface, and a second wiring portion located on the rear surface; a light emitting element electrically connected with the first wiring portion; and a first reflective member covering a lateral surface of the light emitting element and the front surface of the base member. The base member has a recessed portion opened on the rear surface and the bottom surface. The substrate includes a third wiring portion covering an inner wall of the recessed portion and electrically connected with the second wiring portion, and a via in contact with the first wiring portion, the second wiring portion and the third wiring portion.

Abstract: Semiconductor devices and methods of forming thereof are disclosed. A substrate with different device regions defined in the substrate is provided. A deep trench isolation (DTI) structure is formed in the substrate to isolate the different device regions. The DTI structure includes a fill material and a dielectric layer surrounding the fill material in the DTI structure. Local oxidation of the substrate is performed over the DTI structure to form a thermal dielectric layer which overlaps the DTI structure. The thermal dielectric layer which overlaps the DTI structure forms a thick top corner dielectric in the DTI structure.

Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.

Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.

Abstract: An optoelectronic device with a mixture including silicone and a fluoro-organic additive is disclosed. In an embodiment the device includes at least one radiation-emitting or radiation-detecting semiconductor and a mixture including silicone and a fluoro-organic additive. The mixture may be a component of at least one of the following elements: a package body element surrounding the at least one semiconductor at least in places, a radiation-guiding element arranged in a beam path of a radiation emitted by the semiconductor or detected by the semiconductor, a heat-conducting element configured to conduct heat emitted by the semiconductor or received by the semiconductor, or an adhesive element.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: The invention provides a manufacturing method for TFT array substrate and TFT array substrate. The manufacturing method forms a first buffer layer on the substrate; the first buffer layer is disposed with a plurality of arc protrusions or a plurality of arc recesses; then an a-Si layer is formed on the second buffer layer which is formed on the first buffer layer; in the process of forming a polysilicon layer by performing ELA on the a-Si layer, the arc protrusions or the arc recesses can change the optical path of the laser to form an energy gradient in the a-Si layer, so as to increase the grain size in the formed polysilicon layer, reduce the number of grain boundaries, improve the carrier mobility of the TFT device, and improve the electrical properties of the TFT device.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: A method is provided for producing an electrically-powered device and/or component that is embeddable in a solid structural component, and a system, a produced device and/or a produced component is provided. The produced electrically powered device includes an attached autonomous electrical power source in a form of a unique, environmentally-friendly structure configured to transform thermal energy at any temperature above absolute zero to an electric potential without any external stimulus including physical movement or deformation energy. The autonomous electrical power source component provides a mechanism for generating renewable energy as primary power for the electrically-powered device and/or component once an integrated structure including the device and/or component is deployed in an environment that restricts future access to the electrical power source for servicing, recharge, replacement, replenishment or the like.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: Processes for fabricating multi- and monolayer silicene on catalyst metal surfaces by means of plasma-enhanced chemical vapor deposition (PECVD). Silicene is grown by means of PECVD from a starting mixture of H2 and SiH4 having an H2:SiH4 ratio of 100 to 400 on an Ag(111) substrate having a substrate temperature between 20° C. and 290° C., with the deposition being performed for about 10-25 minutes at an RF power between 10 W and 500 W and under a chamber pressure between about 100 mTorr and 1300 mTorr. In most cases, the substrate will be in the form of an Ag(111) film sputtered on a fused silica substrate. A multi-layer silicene film can be formed by extending the deposition time past 25 minutes.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell.