Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: Methods and devices for controlling pressures in microenvironments between a deposition apparatus and a substrate are provided. Each microenvironment is associated with an aperture of the deposition apparatus which can allow for control of the microenvironment.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: Provided is an adhesive composition sheet containing an organic compound and inorganic particles, the adhesive composition sheet including a structure obtained by stacking a layer A that contains at least an organic compound and a layer B that contains an organic compound and inorganic particles, the layer A having a content rate of the organic compound larger than the content rate of the organic compound in the layer B, and the layer A and/or the layer B containing anisotropically shaped inorganic particles. The present invention provides an adhesive composition sheet excellent in thermal conductivity and insulating properties after cured.

Abstract: A radio frequency (RF) switch includes a heating element, a phase-change material (PCM) situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM. The heating element can have a heater line underlying an active segment of the PCM. Alternatively, the heating element can have a split heater lines underlying an active segment of the PCM. The split heater lines increase an area of the active segment of the PCM and reduce a heater-to-PCM parasitic capacitance. A fan-out structure having fan-out metal can connect the heater line to a heater contact. The fan-out structure reduces heat generation outside the active segment of the PCM and reduces a heater contact-to-PCM parasitic capacitance. The fan-out structure can have dielectric segments interspersed between the fan-out metal to reduce dishing.

Abstract: Embodiments of the invention relate to processes for fabricating a smart device (200), e.g. smart card, and configurations for smart card devices with greater reliability and lifespan, and improved finish. In the smart card device comprising of laminated substrate layers (220, 240) interposing a flexible film (230) having conductor pattern thereon, at least one flip chip (250) for operating the smart card device is embedded in a first substrate (220) such that the first substrate provides an encapsulation to the at least one flip chip, wherein the at least one flip chip (250) is arranged at a position in a first vertical plane; and a contact pad (260), for providing electrical connection when the smart card device is inserted into a smart card reader, is arranged at a position in a second vertical plane, wherein the first vertical plane is non-overlapping with the second vertical plane.

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

Abstract: A method for forming a unique, environmentally-friendly micron scale autonomous electrical power source is provided in a configuration that generates renewable energy for use in electronic systems, electronic devices and electronic system components. The configuration includes a first conductor with a facing surface conditioned to have a low work function, a second conductor with a facing surface having a comparatively higher work function, and a dielectric layer, not more than 200 nm thick, sandwiched between the respective facing surfaces of the first conductor and the second conductor. The autonomous electrical power source formed according to the disclosed method is configured to harvest minimal thermal energy from any source in an environment above absolute zero.

Abstract: A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

Abstract: A method includes steps of (a) forming a substrate layer 10 above a support substrate 8 which is transparent, and then a thin-film element above the substrate layer 10; and (b) emitting laser beams La and Lb to a face of the support substrate 8 opposite to another face of the support substrate to which the substrate layer 10 and the thin-film element are formed, and delaminating the substrate layer 10 and the thin-film element from the support substrate 8. In step (b), the laser beams La and Lb are emitted from different directions.

Abstract: The present disclosure provides a light-emitting device, comprising: a light-emitting stack; a first semiconductor layer on the light-emitting stack; a first electrode formed on the first semiconductor layer and comprising an inner segment, an outer segment, and a plurality of extending segments electrically connecting the inner segment with the outer segment.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a second insulating film and a plurality of contacts. The stacked body is provided on the substrate and includes a plurality of electrode films stacked with spacing from each other. An end part of the stacked body is shaped like a staircase in which a terrace is formed in each of the plurality of electrode films. The first insulating film is provided on the end part. The second insulating film is provided on the first insulating film and located along the end part. At least part of the second insulating film extends with inclination. The plurality of contacts extends in a stacking direction of the plurality of electrode films in the first insulating film and the second insulating film and is located on the terraces of the plurality of electrode films.

Abstract: A method of active alignment of a shadow mask to a substrate includes a first alignment by moving the shadow mask and the substrate a first distance in a vertical direction, capturing a first alignment image, determining at least one of a first correction distance and a first rotational correction angle, and aligning the shadow mask and the substrate by moving the first correction distance and rotating the first rotational correction angle. The method further includes performing a first material deposition process on the substrate and continuously capturing a first series of alignment images during the generation of the first material deposition flow. During the generation of the first material deposition flow the first series of alignment images are analyzed to determine a second correction distance and a second rotational correction angle and determining whether second distance and/or rotational correction angle is greater than or equal to a predetermined value to cause a second alignment process to occur.

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

Abstract: A monitoring and deposition control system and method of operation thereof including: a deposition chamber for depositing a material layer on a substrate; a sensor array for monitoring deposition of the material layer for changes in a layer thickness of the material layer during deposition; and a processing unit for adjusting deposition parameters based on the changes in the layer thickness during deposition.

Abstract: A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.