Abstract: Examples herein relate to negative differential resistance devices. An example negative differential resistance device includes a first electrode and a first negative differential resistance device coupled to the first electrode. A second negative differential device is be coupled to the first negative differential resistance device. The second NDR device is different from the first NDR device. A second electrode is coupled to the second NDR device, and is electrically coupled with the first NDR device and the first electrode.

Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.

Abstract: A bonding method is provided. A sheet structure is placed on a substrate surface, and a surface roughness of a surface of the sheet structure is less than or equal to 1.0 micrometer. A carbon nanotube structure is laid on the surface of the sheet structure. Two ends of the carbon nanotube structure are in direct contact with the substrate surface. An organic solvent is added to the two ends of the carbon nanotube structure. An object is laid on the carbon nanotube structure, and a surface of the object being in direct contact with the carbon nanotube structure has a surface roughness less than or equal to 1.0 micrometer.

Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.

Abstract: Described herein are compositions and methods for forming silicon oxide films. In one aspect, the film is deposited from at least one precursor, wherein the at least one precursor has a structure represented by Formula A: wherein R, R1, R2, R3, R4, and R5 are defined herein.

Abstract: A method for producing a semiconductor body is disclosed. In an embodiment, the method includes providing a semiconductor body, applying a first mask layer and a second mask layer to the semiconductor body and forming at least one second mask opening in the second mask layer and at least one recess in the semiconductor body in a region of the at least one first mask opening in the first mask layer, wherein the recess comprises a side face and a bottom face and the recess forms an undercut with the second mask opening. The method further includes applying a passivation layer unpatterned to the second mask layer and to the side face and the bottom face of the at least one recess and removing the passivation layer so that the passivation layer remains at least in part on the side face of the at least one recess.

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.

Abstract: Disclosed is a method for producing a plurality of semiconductor chips (10). A composite (1), which comprises a carrier (4) and a semiconductor layer sequence (2, 3), is provided. Separating trenches (17) are formed in the semiconductor layer sequence (2, 3) along an isolation pattern (16). A filling layer (11) limiting the semiconductor layer sequence (2, 3) toward the separating trenches (17) is applied to a side of the semiconductor layer sequence (2, 3) facing away from the carrier (4). Furthermore, a metal layer (10) adjacent to the filling layer (11) is applied in the separating trenches (17). The semiconductor chips (20) are isolated by removing the metal layer (10) adjacent to the filling layer (11) in the separating trenches (17). Each isolated semiconductor chip (20) has one part of the semiconductor layer sequence (2, 3), and of the filling layer (11). Also disclosed is a semiconductor chip (10).

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

Abstract: The present disclosure describes apparatuses and techniques for self-aligning integrated circuit (IC) dies. In some aspects, a hydrophobic material is deposited on a surface of a substrate to form a pattern on the surface of the substrate. The pattern may expose areas of the substrate surface for placement of IC dies. A water-based solution is then applied to the exposed areas such that droplets form on the exposed areas of the substrate surface. IC dies are placed on the droplets of the water-based solution, which can cause the IC dies to align with the exposed areas of the substrate surface. The droplets are then caused to evaporate such that the IC dies settle on the exposed areas of the substrate surface.

Abstract: A semiconductor package includes a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate, a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate, and an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip, wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess, in a region overlapped with the lower semiconductor chip, and no electrical signal is applied to the dummy wiring layer.

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad.

Abstract: A method for producing a semiconductor body is disclosed. In an embodiment the method includes providing a semiconductor body, applying a first mask layer and a second mask layer to the semiconductor body and forming at least one second mask opening in the second mask layer and at least one recess in the semiconductor body in a region of the at least one first mask opening in the first mask layer, wherein the recess comprises a side face and a bottom face and the recess forms an undercut with the second mask opening, when viewed from the first mask opening. The method further includes applying a contact layer to the first mask layer and the bottom face of the at least one recess using a directional deposition method and applying a passivation layer to the side face of the at least one recess.

Abstract: Disclosed are a single-source precursor for synthesizing metal chalcogenide nanoparticles for producing a light absorption layer of solar cells comprising a Group VI element linked as a ligand to any one metal selected from the group consisting of copper (Cu), zinc (Zn) and tin (Sn), metal chalcogenide nanoparticles produced by heat-treating at least one type of the single-source precursor, a method of preparing the same, a thin film produced using the same and a method of producing the thin film.

Abstract: A method of manufacturing a plurality of light emitting devices includes providing a collective substrate including a plurality of packages, each of the packages including: a recess defined by lateral surfaces and a bottom surface, a first electrode and a second electrode that are disposed at the bottom surface of the recess, and a light-reflective first resin member surrounding an element-mounting region of the bottom surface of the recess, the first resin member having an upper surface located at a position higher than the element-mounting region; mounting a light emitting element in the element-mounting region; forming a light-reflective second resin member having a light reflective surface; and singulating the collective substrate to obtain the plurality of light emitting devices.

Abstract: Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.

Abstract: A power system has a single-side-cooled power module including a contiguous five-layer substrate of two insulative layers interleaved with three conductive layers. A center one of the conductive layers is partitioned to define discrete spaced apart positive terminal and output terminal portions, and an outer of the conductive layers defines a negative terminal portion such that the positive terminal and negative terminal portions overlap. The power system also has semiconductors respectively in direct contact with the positive terminal and output terminal portions without directly contacting the other layers.

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

Abstract: Provided is a display apparatus capable of reducing generation of defects during manufacturing of the display apparatus or while in use after being manufactured. The display apparatus includes a substrate including a bending area between a first area and a second area, the substrate being bent in the bending area about a bending axis; an inorganic insulating layer over the substrate and including a first feature that is either a first opening or a first groove, the first feature positioned to correspond to the bending area; and an organic material layer at least partially filling the first feature, and including a second feature that is a second opening or a second groove, the second feature extending along an edge of the substrate.

Abstract: A field effect transistor includes a fin having a stack of nanowire-like channel regions including at least first and a second nanowire-like channel regions, source and drain electrodes on opposite sides of the fin, a dielectric separation region including a dielectric material between the first and second nanowire-like channel regions, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer of the gate stack does not extend between the first and second nanowire-like channel regions.