Patents Examined by Bruce Breneman
  • Patent number: 5996213
    Abstract: A method of manufacturing a thin film merged magnetic head including an inductive write structure and a magnetoresistive sensor uses a patterned protection layer to protect a second shield/bottom pole layer in regions spaced from the pole tip of the inductive write structure. A window is provided in the protection layer. During manufacture, the configuration comprises a first shield layer, a magnetoresistive element, a second shield layer serving as a bottom pole, a protection layer, a protection window, a write gap, a top pole, and a pole tip structure. The use of a protection layer and window results in the formation of channels in the second shield layer adjacent to a pedestal that supports the inductive write structure. The channels prevent magnetic flux from extending toward the second shield layer beyond the width of the pole tip structure. This structure reduces side writing with a consequent improvement in off-track performance.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: December 7, 1999
    Assignee: Read-Rite Corporation
    Inventors: Yong Shen, Bertha Higa-Baral, Lien-Chang Wang
  • Patent number: 5996595
    Abstract: Semiconductor wafers are positioned in a cleaning tank and subjected to sequential flows of one or more highly diluted cleaning solutions that are injected from the lower end of the tank and allowed to overflow at the upper end. One solution comprises one part ammonium hydroxide, two parts hydrogen peroxide, and 300-600 parts deionized water together with a trace of high purity surfactant. Rinsing water is flowed through the tank after the first solution is dumped. A second solution comprises highly dilute hydrofluoric acid. A third solution is more dilute than the first solution. A fourth solution contains hydrochloric acid greatly diluted with deionized water. The cleaning tank is provided with a megasonic generator in its lower portion for selective application of megasonic energy. Quick dump valves in the tank bottom enable the solutions to be quickly dumped followed by one or more rinse steps, including a quick refill while spraying and then dumping of the rinsing water.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: December 7, 1999
    Assignee: Verteq, Inc.
    Inventors: Michael B. Olesen, Mario E. Bran
  • Patent number: 5997650
    Abstract: An apparatus for adjusting the tension on a heating filament in a reactor used in carbon deposition on a substrate via chemical-vapor deposition is disclosed, as is a method for preventing breakage of the filaments during operation. The apparatus comprises a force regulator attached to an array of heating filaments. Preferably, the force regulator is adjustable and is adjusted prior to reactor operation and/or periodically or continuously as the filaments lengthen due to carburization in the carbon-vapor environment of the reactor. The adjustable force regulator attached to an array of filaments enables effective regulation of the force on a filament during reactor operation and provides an easily-maintained reactor with quick turn-around time between cycles of use.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: December 7, 1999
    Assignee: Sp.sup.3, Inc.
    Inventors: James E. Herlinger, David K. Studley, Jerry W. Zimmer
  • Patent number: 5994227
    Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: November 30, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Takuji Oda, Yuichi Yokoyama, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Patent number: 5993680
    Abstract: The present invention provides a method of removing a hard carbon film (15) from the inner surface of a guide bush (11) through etching. The method comprises the steps of inserting an auxiliary electrode (71) in the center bore (11j) of the guide bush (11) wherein the hard carbon film (15) is formed over the inner surface thereof, in sliding contact with a workpiece, disposing the guide bush (11) with the auxiliary electrode inserted in the center bore thereof in a vacuum vessel (61) provided with an anode (79) and a filament (81) therein, grounding the auxiliary electrode (71) or applying a positive DC voltage thereto, and producing a plasma in the vacuum vessel (61) by feeding an oxygen-containing gas therein and applying a DC voltage to the anode (79) and an AC voltage to the filament (81) respectively, while applying a DC voltage to the guide bush (11) after evacuating the vacuum vessel (61).
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: November 30, 1999
    Assignee: Citizen Watch Co., Ltd.
    Inventors: Osamu Sugiyama, Yukio Miya, Ryota Koike, Takashi Toida, Toshiichi Sekine
  • Patent number: 5993677
    Abstract: A thin film is transferred from an initial substrate onto a final substrate. The process includes the following successive stages: joining of the thin film (112) onto a handle substrate (120) comprising a cleavage zone, elimination of the initial substrate, joining of the thin film (112) with a final substrate (132), and cleavage of the handle substrate (120) following the cleavage zone. The cleavage zone includes a film of micro-bubbles formed by ion implantation. The invention has, in particular, applications in the fabrication of three-dimensional structures of integrated circuits.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: November 30, 1999
    Assignee: Commissariat a L'Energie Atomique
    Inventors: Beatrice Biasse, Michel Bruel, Marc Zussy
  • Patent number: 5994238
    Abstract: A method for fabricating a semiconductor device is characterized by using a mixture chemical comprising ozone gas, anhydrous HF gas and deionized water vapor as an etchant for etching an oxide- and silicon-exposed wafer, whereby the etch selection ratio of oxide to silicon can be controlled according to necessity, so that the production yield and reliability of semiconductor device are improved. During etching of a wafer with exposed thermal oxide and exposed silicon, the etch rate ratio of oxide to silicon is controlled by changing the relative flow rates of the ozone gas, anhydrous HF gas and deionized water vapor.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: November 30, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Chang Seo Park
  • Patent number: 5993679
    Abstract: A method of cleaning metallic films built up within a thin film deposition apparatus is disclosed. The method includes an oxidation step to oxidize the metallic film and produce a film of the oxide thereof, a complexing step to complex the oxide film and produce a complex thereof, and a sublimation step to sublimate the complex. The conditions of these cleaning steps are set so that the oxidation step is the rate-determining step.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: November 30, 1999
    Assignee: Anelva Corporation
    Inventors: Tomoaki Koide, Akiko Kobayashi, Ko Sang Tae, Atsushi Sekiguchi, Osamu Okada
  • Patent number: 5993557
    Abstract: An apparatus for growing a high-quality single-crystalline semiconductor film on a substrate based on vapor phase growth while rotating the substrate and preventing micro-particles generated by a rotary drive unit from adhering onto the major plane of the substrate. The substrate 2 set inside the reaction chamber 21 is rotated using the rotary drive unit 7, a reaction gas 10 is fed to the major plane side of the substrate 2, a purge gas 3a is fed to the back space of the substrate in the reaction to chamber 21 to replace a space 11a with a carrier gas atmosphere, where the rotary drive unit 7 is located in the purge gas discharge section 13, a purge gas discharge duct 12 connected to the purge gas discharge section, and further to the purge gas discharge duct 12 is connected a gas flow controller 8, and serially in the downstream side thereof is connected an evacuation pump 9.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: November 30, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Munenori Tomita, Masanori Mayuzumi, Hitoshi Habuka
  • Patent number: 5994225
    Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: November 30, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Tsung Liu, Tsung-Yuan Hung, Bill Hsu
  • Patent number: 5993597
    Abstract: The present invention provides:a plasma etching electrode made of single-crystal silicon, which has an electric resistance of 0.0001-40 .OMEGA.cm, whose crystal faces are (100), which is doped with boron or phosphorus, whose surface has been subjected to an etching treatment with an acid, and which has been subjected to a heat treatment in vacuum, or a plasma etching electrode made of polycrystalline silicon, which has an electric resistance of 0.0001-40 .OMEGA.cm, which is doped with boron or phosphorus, whose surface has been subjected to an etching treatment with an acid, and which has been subjected to a heat treatment in vacuum, anda process for producing a plasma etching electrode, which comprises doping metallic silicon with boron or phosphorus, subjecting the surface of the resulting material to an etching treatment with an acid, and subjecting the surface-etched material to a heat treatment in vacuum.With the plasma etching electrode, dust generation is minimized and uniform etching can be realized.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: November 30, 1999
    Assignee: Nisshinbo Industries, Inc.
    Inventors: Kazuo Saito, Yasushi Mochizuki, Akira Yamaguchi
  • Patent number: 5989444
    Abstract: Fluid bearings, vacuum chucks and methods for producing these devices. One example of a method for forming a fluid bearing includes forming a plate having a face surface and a bonding surface, coupling a first side of a body to the bonding surface, placing the face surface of the plate against a predetermined surface, and generating a pressure difference to conform the face surface to the predetermined surface. One example of a fluid bearing of the invention includes a plate support and a flexible bearing plate having a bonding surface which is attached to the plate support with an adhesive which is flexible before hardening. The flexible bearing plate conforms to a predetermined surface during a portion of the time that the adhesive hardens. Examples of vacuum chucks, and methods for forming vacuum chucks, and other aspects of the invention are described.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: November 23, 1999
    Inventor: Marek Zywno
  • Patent number: 5989345
    Abstract: A process-gas supply apparatus for supplying a process gas to a process chamber in which a predetermined processing using the process gas is applied to the object set therein, which comprising a process-gas source for supplying a process gas, a carrier gas source filled with a carrier gas, at least one gas storing section having a predetermined volume and to be filled with the process gas, a carrier-gas introducing pipe connecting the carrier gas source to the process chamber to introduce the carrier gas from the carrier gas source to the process chamber, a process-gas releasing pipe connected to the process-gas source, a process-gas filling circuit having at least one pipe which connects the at least one gas storing section to the process-gas releasing pipe and is provided with at least one open/shut valve, a process gas releasing circuit having at least one pipe which connects the gas storing section to the carrier-gas introducing pipe and is provided with at least one open/shut valve, a controlling section
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: November 23, 1999
    Assignee: Tokyo Electron Limited
    Inventor: Tatsuo Hatano
  • Patent number: 5990019
    Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a vapor phase solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning vapor phase solutions include about 1% water, about 5% hydrogen fluoride, and about 5% ammonias. The vapor phase solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning vapor phase solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 500 PPMV water, about 2% hydrogen fluoride, and about 2% ammonia is most preferred.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: November 23, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kevin James Torek, Whonchee Lee, Richard C. Hawthorne
  • Patent number: 5989442
    Abstract: Method for wet etching where proper arrangements of the substrates during the growth of the insulation layer is adopted. An insulation layer is prepared on the surface of a substrate at the area where thin film circuits are positioned. On the surfaces of the substrate where the thin film circuits are not positioned are prepared protective layers. During the wet etching the attack by the etchant may be avoided. The material of the insulation layer and the protection layer may be the same. The material of the protection layer may be the photo-resistant used in the wet etching process. The invention also disclosed circuit components prepared with the wet etching of this invention.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: November 23, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Hsien-Fen Hsieh, Ming-Teh Hsu
  • Patent number: 5990003
    Abstract: There is provided a method of fabricating a semiconductor, including the steps, in sequence, of (a) forming a first interlayer insulating film over a semiconductor substrate, (b) forming an electrically conductive contact hole in the first interlayer insulating film, (c) forming a second interlayer insulating film over the first interlayer insulating film, (d) forming a photosensitive organic film over the second interlayer insulating film, (e) forming a via-hole passing through the photosensitive organic film and the second interlayer insulating film, the via-hole being in vertical alignment with the contact hole, (f) forming a film so that the film covers the photosensitive organic film therewith and fills the via-hole therewith, (g) exposing the film to plasma so that a portion of the film lying over the photosensitive organic film is removed, (h) removing both the photosensitive organic film and the film remaining in the via-hole, and (i) forming a wire above the via-hole.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: November 23, 1999
    Assignee: NEC Corporation
    Inventor: Noriaki Oda
  • Patent number: 5988104
    Abstract: The present invention provides a plasma treatment system having a reaction chamber in which a plasma is generated to be irradiated onto a sample held on a sample holder in the reaction chamber. The reaction chamber has a top covered by a dielectric plate. The plasma treatment system also has an opposite electrode having a plurality of windows through which microwave is transmitted into the reaction chamber for causing the plasma, wherein the opposite electrode is provided over a top surface of the dielectric plate so that the opposite electrode is separated by the dielectric plate from the plasma generated in the reaction chamber.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: November 23, 1999
    Assignee: NEC Corporation
    Inventor: Hidetaka Nambu
  • Patent number: 5989445
    Abstract: Microchannels for conducting and expelling a fluid are embedded in a surface of a silicon substrate. A channel seal is made of plural cross structures formed integrally with the silicon substrate. The cross structures are arranged sequentially over each channel, each cross structure having a chevron shape. The microchannel is sealed by oxidizing at least partially the cross structures, whereby the spaces therebetween are filled. A dielectric seal which overlies the thermally oxidized cross structures forms a complete seal and a substantially planar top surface to the silicon substrate. The dielectric seal is formed of a low pressure chemical vapor deposition (LPCVD) dielectric layer. The channel is useful in the production of an ink jet print in head, and has a polysilicon heater overlying the dielectric seal. A current passing through the heater causes a corresponding increase in the temperature of the ink in the microchannel, causing same to be expelled therefreom.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: November 23, 1999
    Assignee: The Regents of the University of Michigan
    Inventors: Kensall D. Wise, Jingkuang Chen
  • Patent number: 5989346
    Abstract: In a semiconductor processing apparatus, an external transfer mechanism transfers substrates between a cassette for storing a plurality of target substrates by vertically arranging the substrates at first intervals, and a processing section for performing semiconductor processing for the substrates. The external transfer mechanism has first and second arms defining first and second support surfaces each of which can support one of the substrates and capable of vertically moving relative to each other. An interval adjuster is disposed to adjust an interval in a vertical direction between the first and second support surfaces by moving the first and second arms relative to each other. An arm driving base is disposed to move the first and second arms between a position at which the first and second arms oppose the cassette and a position at which the first and second arms oppose the processing section.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: November 23, 1999
    Assignee: Tokyo Electron Limited
    Inventor: Tsutomu Hiroki
  • Patent number: 5983829
    Abstract: A plasma process apparatus comprises a plasma process chamber, substrate-to-be-processed supporting means for supporting a substrate to be processed, provided in the process chamber, gas introducing means, gas evacuation means, microwave introducing means using an endless circular waveguide having a plurality of slots arranged around the process chamber, and radio frequency power supplying means for supplying radio frequency power to the substrate supporting means. The above arrangement permits a uniform plasma to be generated in high density and in a large area even under the low-pressure condition of about 1 mTorr without using a magnetic field, thus enabling etching of large-area substrates in super fine patterns and at high speed.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: November 16, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobumasa Suzuki