Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A supporting substrate is prepared. The supporting substrate has a chip mounting area, and a plurality of penetrating slits around the chip mounting area. At least a stack of semiconductor chips is formed over the chip mounting area. A first sealing member is formed, which seals the stack of semiconductor chips without the first sealing member filling the plurality of penetrating slits.

Abstract: A method of depositing encapsulant on a line of wire bonds to a die is described, the die having a back surface in contact with the support structure and an active surface opposing the back surface, the active surface having electrical contact pads and functional elements spaced from the contact pads. The method involves the steps of providing a die mounted to the support structure, positioning a barrier between the contact pads and the functional elements, the barrier being proximate to, but spaced from the active surface, depositing a bead of encapsulant onto the electrical contact pads while the barrier remains stationary such that the barrier prevents the encapsulant from contacting the functional elements, removing the barrier when the bead of encapsulant has been deposited. The fluidic resistance generated by the gap between the barrier and the active surface means that the amount of encapsulant that flows into the gap and onto the active surface is almost constant.

Abstract: A rotor has a central shaft having a central longitudinal axis. The rotor has a longitudinal stack of a plurality of disks surrounding the shaft. An aft hub couples the stack to the shaft. The aft hub has a proximal portion and a distal portion. The distal portion tapers at a lower characteristic half angle than does the proximal portion.

Abstract: The production method of a photoelectric conversion device comprises adding a chalcogenide powder of a group-IIIB element to an organic solvent including a single source precursor containing a group-IB element, a group-IIIB element, and a chalcogen element to prepare a solution for forming a semiconductor, and forming a semiconductor containing a group-I-III-VI compound by use of the solution for forming a semiconductor.

Abstract: This invention relates to an electric cartridge heater and a method of operation, suitable for use in producing high purity silicon in solar cells or solar modules. The apparatus includes a single-piece elongated heater bar having a length, a first end, and a second end. The apparatus also includes a slot beginning at the first end and running a portion of the length, and the slot dividing the heater bar into a first arm and a second arm. An elbow at the second end joins the first arm and the second arm together. The apparatus also includes a first electrode in electrical communication with the first arm, and a second electrode in electrical communication with the second arm.

Abstract: A method of determining at least one rotation parameter of a wind turbine rotor rotating with a rotation speed and a phase is provided. The method includes: measuring an effective centrifugal force acting in a first pre-determined direction, which is defined in a co-ordinate system rotating synchronously with the rotor, on at least one reference object located in or at the rotor, establishing a first angular frequency representing the rotation speed of the rotor on the basis of variations in the measured effective centrifugal force due to gravitational force, establishing a second angular frequency representing the rotation speed of the rotor by use of at least one yaw rate gyro, and establishing the value of the rotation speed as the rotational parameter by correcting the second angular frequency by comparing it to the first angular frequency.

Abstract: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The individual dies include integrated circuitry and a terminal electrically coupled to the integrated circuitry. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with the terminal. The first opening has a generally annular cross-sectional profile and separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening aligned with at least a portion of the terminal.

Abstract: A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.

Abstract: A method of manufacturing a flexible display device is disclosed. The method includes arranging a first substrate having a plurality of depression units, forming a first plastic film in each of the plurality of depression units, forming a thin film transistor (TFT) on the first plastic film, forming a display device on the TFT, where the display device is configured to be electrically connected to the TFT, encapsulating an upper portion of the display device, cutting the first substrate, and separating the first substrate from the first plastic film.

Abstract: A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

Abstract: A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer material are selected. The buffer layer material is deposited on the substrate, the phase change material is deposited on the buffer layer, and the cladding layer material is deposited on the phase change material to form a memory cell element. The thickness of the phase change material is preferably less than 30 nm and more preferably less than 10 nm. The recrystallization time of the phase change material of the memory cell element is determined. If the recrystallization time is not less than a length of time X, these steps are repeated while changing at least one of the selected materials and material thicknesses.

Abstract: A horizontal axis wind turbine rotor assembly utilizes rotor blades having the aerodynamic characteristics of low aspect ratio lifting bodies. The aerodynamic characteristics of low aspect ratio lifting bodies at typical operating wind velocities permits high energy conversion efficiencies throughout a wide range of wind speeds.

Abstract: The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract: An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.

Abstract: An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via may be electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other.

Abstract: A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.

Abstract: A method of determining at least one rotation parameter of a wind turbine rotor rotating with a rotation speed and a phase is provided. The method comprises the steps of: measuring an effective centrifugal force acting in a first pre-determined direction, which is defined in a co-ordinate system rotating synchronously with the rotor, on at least one reference object located in or at the rotor, establishing a first angular frequency representing the rotation speed of the rotor on the basis of variations in the measured effective centrifugal force due to gravitational force, establishing a second angular frequency representing the rotation speed of the rotor by use of at least one yaw rate gyro, and establishing the value of the rotation speed as the rotational parameter by correcting the second angular frequency by comparing it to the first angular frequency.

Abstract: An improved, lower cost method of processing substrates, such as to create solar cells, is disclosed. The doped regions are created on the substrate, using a mask or without the use of lithography or masks. After the implantation is complete, visual recognition is used to determine the exact region that was implanted. This information can then be used by subsequent process steps to crate a suitable metallization layer and provide alignment information. These techniques can also be used in other ion implanter applications. In another aspect, a dot pattern selective emitter is created and imaging is used to determine the appropriate metallization layer.

Abstract: In a method of forming a pattern, a mold layer having an opening is formed on a substrate. A conductive layer is formed on the mold layer having the opening, the conductive layer having a substantially uniform thickness. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern having a cross-linked structure of water-soluble copolymers including a repeating unit of N-vinyl-2-pyrrolidone and a repeating unit of acrylate. An upper portion of the conductive layer exposed over the buffer layer pattern is etched. Accordingly, a conductive pattern for a semiconductor device is formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.