Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.

Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask.

Abstract: One illustrative method disclosed herein includes forming a seed layer above a structure, forming a nucleation layer on the seed layer, forming a plurality of spaced-apart, vertically oriented alloy structures that are comprised of materials from the seed layer and the nucleation layer, forming a sacrificial material layer above the nucleation layer and around the alloy structures, performing an etching process to remove the alloy structures and portions of the seed layer so as to thereby define a plurality of openings, forming an initial masking structure in each of the openings, performing an etching process to remove the sacrificial material layer and the nucleation layer so as to thereby expose the structure and define a masking layer comprised of the initial masking structures, and performing at least one process operation on the structure through the masking layer.

Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

Abstract: A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F2, or when a special structure is employed for a cell transistor, an area per memory cell less than or equal to 4F2 can be achieved.

Abstract: A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines.

Abstract: Provided are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a substrate, a first semiconductor layer containing indium (In) over the substrate, and a light emitting structure over the first semiconductor layer. A dislocation mode is disposed on a top surface of the first semiconductor layer.

Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.

Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.

Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.

Abstract: Disclosed is a light emitting device a light transmissive substrate, a light emitting structure disposed on the light transmissive substrate, comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a conductive layer disposed on the second conductive type semiconductor layer, a first electrode part disposed on the conductive layer, with at least predetermined region in contact with the first conductive type semiconductor layer, passing through the conductive layer, the second conductive type semiconductor layer and the active, and a first insulation layer disposed between the conductive layer and the first electrode part, between the second conductive type semiconductor layer and the first electrode part and between the active layer and the first electrode part.

Abstract: In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.

Abstract: An electrical connection includes a first wire having one end stitch bonded to a surface, such as the lead finger of a lead frame or the connection pad of a substrate. A second wire has a first end attached to the surface on a first side of the first wire and a second end attached to the surface on a second, opposing side of the first wire. The second wire acts as a brace that prevents the first wire from lifting off of the surface. If necessary, a third wire can be added that, like the second wire, acts as a brace to prevent the first wire from lifting off of the surface.

Abstract: A method of forming contact openings in the fabrication of integrated circuitry includes forming a mask which includes at least one of photoresist and amorphous carbon received over a plurality of spaced conductive line constructions. The conductive line constructions include insulative caps and insulative sidewalls. The mask includes a plurality of spaced lines and trench spaces between adjacent of the spaced lines. The spaced lines and the trench spaces angle relative to the conductive line constructions. The trench spaces are received over node locations which are received between adjacent of the conductive line constructions. The at least one of photoresist and amorphous carbon is treated with a plasma to reduce lateral width of the spaced lines and to increase lateral width of the trench spaces. After the treating, contact openings are etched to the node locations selectively relative to the insulative caps and the insulative sidewalls.

Abstract: A device and method improving luminous efficiency and luminescent color in an organic EL display panel used in electronic devices such as televisions or the like by making it easy to adjust the difference in film thickness between layers of different luminescent colors, such as intermediate layers, when the intermediate layers and light-emitting layers are formed by a wet method. By varying by color the volume of a contact hole formed in an interlayer insulation film, which is a lower layer of an organic EL element, the volume of a concavity in each anode plate is adjusted. When ink that includes material for the intermediate layer or the like is sprayed by an inkjet method, the film thickness of the intermediate layer or the like changes in accordance with the amount of ink filing the concavity.

Abstract: A method of manufacturing a semiconductor apparatus includes forming back surface electrode 4 on back surface of semiconductor wafer 20, that bends convexly toward the front surface side due to back surface electrode 4 being formed; treating the back surface with a plasma for removing the deposits on the back surface; sticking removable adhesive tape 23 to the back surface along the warp thereof for maintaining the bending state of semiconductor wafer 20 after the step of sticking; electrolessly plating to form film 26 on the front surface of semiconductor wafer 20; peeling off removable adhesive tape 23; cutting out semiconductor chips; and mounting the semiconductor chip by bonding with a solder for manufacturing a semiconductor apparatus. The manufacturing method prevents external appearance anomalies from occurring on the back surface electrode, improves the reliability, and allows manufacture of the semiconductor apparatuses with a high throughput of non-defective products.

Abstract: A fluid energy conversion device comprising a plurality of adjacent fluid catching modules that may be disposed about a central drive shaft, wherein the central drive shaft may be rotatably secured to a support frame. Each of the plurality of adjacent fluid catching modules may comprise two intake elements having a first fluid capturing aperture, an overlap portion, and a second fluid capturing aperture facing a direction opposite to that of the first fluid catching aperture. Adjacent fluid catching modules may be offset from each other by a predetermined angular position, thus allowing for at least one fluid catching aperture to be facing a directional fluid energy source at all times. The plurality of fluid catching modules may comprise different widths and form an overall conical configuration or the plurality of fluid catching modules may comprise equivalent widths and form an overall cylindrical configuration.

Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.