Abstract: A heating and cooling system for a wind turbine is provided and includes a gearbox, gearbox heat exchanger, generator, generator heat exchanger, and a cooling duct. The cooling duct is connected to the gearbox and generator heat exchangers, and is used to transport air across both heat exchangers to cool the gearbox and generator.
Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
Abstract: A method of manufacturing a photoelectric conversion device having a semiconductor substrate, comprises a first step of forming an insulating film on the semiconductor substrate, a second step of forming first holes in the insulating film, a third step of forming, in the insulating film, second holes shallower than the first holes, a fourth step of forming electrically conductive portions by embedding an electrically conductive material in the first holes, and forming planarization assisting portions by embedding the electrically conductive material in the second holes, and a fifth step of polishing the electrically conductive portions, the insulating film, and the planarization assisting portions until the planarization assisting portions are removed, thereby planarizing upper surfaces of the electrically conductive portions and the insulating film.
Abstract: A method of making a semiconductor chip assembly includes providing a post and a base that include a copper surface layer and an aluminum core, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive into and upward in a gap located in the aperture between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.
Abstract: Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer pattern, forming a pair of recesses exposing sides of the spacer pattern by removing a portion of the insulating layer pattern, and/or filling a conductive material in the recesses.
Type:
Grant
Filed:
August 18, 2008
Date of Patent:
April 27, 2010
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Jeong-ho Lee, Young-hoon Park, Sang-il Jung, Ui-sik Kim, Jun-seok Yang
Abstract: A process for making a MCSFET includes providing a first implant through a first side of an elongated stack, and then providing a second implant through a second side of the stack. The first implant has a dose different than the dose of the second implant, so that final dopant concentrations in the first and second sides differ and the transistor has two threshold voltages Vt1, Vt2.
Type:
Grant
Filed:
January 26, 2009
Date of Patent:
March 23, 2010
Assignee:
International Business Machines Corporation
Inventors:
Xu Ouyang, Louis Lu-Chen Hsu, Xinhui Wang, Haizhou Yin
Abstract: The present subject matter includes a capacitor stack having a plurality of anode layers, and a plurality of cathodic metal substrates partially coated in a titanium coating. Cathode portions lacking titanium enable weld interconnections which are substantially free of titanium, improving capacitor properties. In some embodiments, anodes are interspersed among cathodes, and are electrically separated from the cathodes, with portions of cathode material attached to the welding area of the anode. These portions of the cathode material are no longer electrically connected to the cathode. As the anode and these cathode portions are welded and aged, leakage current is reduced due to improved oxide growth in the welding area due to the absence of titanium.
Type:
Grant
Filed:
March 13, 2008
Date of Patent:
March 23, 2010
Assignee:
Cardiac Pacemakers, Inc.
Inventors:
James M. Poplett, Jeannette C. Polkinghorne, Gregory J. Sherwood
Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.
Type:
Grant
Filed:
October 5, 2007
Date of Patent:
March 23, 2010
Assignee:
QuNano AB
Inventors:
Lars Ivar Samuelson, Bjorn Jonas Ohlsson
Abstract: A method of applying encapsulant to a die mounted to a support structure by providing a die mounted to the support structure, the die having a back surface in contact with the support structure and an active surface opposing the back surface, the active surface having electrical contact pads, positioning a barrier proximate the electrical contact pads and spaced from the active surface to define a gap and, depositing a bead of encapsulant onto the electrical contact pads such that one side of the bead contacts the barrier and a portion of the bead extends into the gap and onto the active surface. Placing a barrier over the active surface so that it defines a narrow gap allows the geometry of the encapsulant front (the line of contact between the encapsulant and the active surface) can be more closely controlled. Any variation in the flowrate of encapsulant from the needle tends to cause bulges or valleys in the height of the bead and or the PCB side of the bead.
Type:
Grant
Filed:
September 25, 2007
Date of Patent:
February 9, 2010
Assignee:
Silverbrook Research Pty Ltd
Inventors:
Laval Chung-Long-Shan, Kiangkai Tankongchumruskul, Kia Silverbrook
Abstract: A method of applying encapsulant to wire bonds between a die and conductors on a supporting substrate, by forming a bead of the encapsulant on a profiling surface, positioning the profiling surface such that the bead contacts the die and, moving the profiling surface relative to the die to cover the wire bonds with the encapsulant. Wiping the encapsulant over the wire bonds with a profiling surface provides control of the encapsulant front as well as the height of the encapsulant relative to the die. The movement of the profiling surface relative to the die can closely controlled to shape the encapsulant to a desired form. Using the example of a printhead die, the encapsulant can be shaped to present an inclined face rising from the nozzle surface to a high point over the wire bonds. This can be used by the printhead maintenance facilities to maintain contact pressure on the wiping mechanism.
Type:
Grant
Filed:
September 25, 2007
Date of Patent:
November 17, 2009
Assignee:
Silverbrook Research Pty Ltd
Inventors:
Laval Chung-Long-Shan, Kiangkai Tankongchumruskul, Kia Silverbrook
Abstract: A method for forming a semiconductor device is provided. More specifically, a method for forming a bulb-shaped portion of a bulb-shaped recess gate is provided to overcome an etching process margin reduction caused by a spacer oxide film formed on sidewalls of a recess and thickly laminated to a lower part of a recess. In one aspect, a buffer dielectric film pattern is formed additionally by a plasma enhanced chemical vapor deposition (PECVD) process over a hard mask pattern, so that a sufficient process margin used for forming the bulb-shaped portion is ensured and a process margin for forming a semiconductor device is increased.
Abstract: A switching element includes a bubble chamber, a heater and a heat conductor. The bubble chamber holds fluid. The bubble chamber includes a trench within a planar light circuit and includes a trench within an integrated circuit attached to the planar light circuit. The heater is located under the trench within the integrated circuit. The heat conductor is attached to the integrated circuit. The heat conductor is located within the trench within the integrated circuit. A portion of the heat conductor is in close proximity to the heater. The heat conductor is more heat conductive than the fluid within the bubble chamber.
Type:
Grant
Filed:
March 12, 2008
Date of Patent:
September 29, 2009
Assignee:
Avago Technologies Fiber IP (Singapore) Pte. Ltd.