Abstract: A block phase estimator include a phase averaging circuit. A first embodiment of the phase averaging circuit includes a phase differencing circuit coupled to an averager input, a first modulo circuit coupled to the phase differencing circuit, a filter coupled to the first modulo circuit, and a summation circuit having an positive input and a negative input, the positive input being coupled to the averager input, the negative input being coupled to the filter. The phase averaging circuit further includes a second modulo circuit coupled to the summation circuit. An alternative embodiment of the phase averaging circuit includes a delay line having a plurality of taps coupled to an averager input and a plurality of first subtractor circuits, a first input of each first subtractor circuit being coupled to the averager input, a second input of each first subtractor circuit being coupled to a corresponding tap of the plurality of taps.

Abstract: A communications system 10 having an Asymmetric Digital Subscriber Line (ADSL) transceiver (24) is provided which may be configured either as a central office or a remote terminal in a system. The transceiver (24) operates in a listen/report idle state to report line activity to a host processor (22) prior to being configured as a central office or remote terminal. The host processor configures the transceiver (24) as a central office, remote terminal, or as otherwise specified based on the line activity.

Abstract: An adaptive high speed data transmission system is described. In one aspect, the transmitter for this system employs a plurality of transmit antennas which have controllable offsets. The transmitter also includes signal coding circuitry suitable for use to address transmission impairments due to fast fading in the transmission channel. At the receiver, the received signal is analyzed to determine the fading characteristics of the channel. Where slow fading is detected, the offsets are employed to convert the slow fading into fast fading. The channel characteristics are continually resampled and these characteristics are used to adjust the transmitter and the receiver to achieve optimal transmission speed.

Abstract: A system and method for transmitting information in which a relatively narrowband signal is transmitted followed by the transmission of a relatively wideband signal. The narrowband signal may be used by the receiver to alert the receiver to the upcoming wideband signal. In a system in which the transmissions occur asynchronously to the receiver, the receiver may be less complicated because the receiver is provided with an indication of the time and/or the center frequency of the wideband signal. Either the narrowband signal or the wideband signal may be used to transmit information from the transmitting device to the receiver. The system and method find particular advantage in tracking and locating systems in which a plurality of tags asynchronously transmit information and/or location information to a receiver or a set of receivers.

Abstract: Method and apparatus for encoding digital information to be recorded on a magnetic medium is disclosed. The invention provides for receiving a sequence of (2.sup.m n+d) user bits, mapping the sequence of user bits to 2.sup.m dc-free codewords, and recording the 2.sup.m dc-free codewords on a magnetic medium. A modulation coder, which includes a memory containing multiple non-intersecting subconstellations of dc-free codewords, performs the mapping in a non-equiprobable manner such that a particular codeword from a larger subconstellation is more likely to be used than a particular codeword from a smaller constellation. Less desirable codewords, such as those containing relatively long strings of bits having the same value, are assigned to the smaller subconstellations, thereby lessening the likelihood of loss of timing and gain parameters in the system, as well as maximizing the transmission rate and efficient use of the set of possible dc-free sequences of a given length.

Abstract: Besides a frequency-phase comparator for input and VCO signals, a filter for a frequency-phase difference signal, and a VCO controlled by a filter output signal to produce a phase locked VCO signal, a PLL circuit comprises a VCO controller for controlling an oscillation frequency range of the VCO when the input and the VCO signals are continuously in collapse of synchronism longer than a predetermined time interval, such as a pull-in time of the PLL circuit, with the collapse detected by the comparator. Preferably, the VCO comprises an inverter loop, each inverter delay controlled by the filter output signal and a loop length controlled by a VCO control signal.

Abstract: A system and method using a Costas loop to effect accelerated convergence with minimal system complexity. The system comprises an in-phase-limiter and a quadrature-phase limiter, operatively coupled to an EXCLUSIVE-OR gate, for exclusively-ORing an in-phase-sign signal and a quadrature-phase-sign signal to output a first error signal, responsive to the signals having same signs, or a second error signal, responsive to the signals having different signs. An AGC circuit, operatively coupled to an output of the EXCLUSIVE-OR gate, increases and decreases a voltage level of an AGC signal responsive to two consecutive first or second error signals and consecutive dissimilar error signals, respectively. A voltage-controlled oscillator, operatively coupled to an output of the AGC circuit and responsive to the increased or decreased voltage level, changes the frequency of a voltage-controlled-oscillator output signal.

Abstract: A framing and voice decoder part outputs an error information. An error ratio monitoring part monitors a bit error ratio based on the error information. A sampling rate changing part decides a sampling rate based on the bit error ratio and changes a number of bits of each shift register in the differential detector part to adapt the sampling rate. A sampling clock selector part selects one clock signal among four different frequency clock signals based on the decision of the sampling rate changing part and gives selected clock signal to the differential detector part as a sampling clock. The differential detector part makes demodulation in DQPSK (Differential Quadrilateral Phase Shift Keying). Since the error ratio is always maintained within a predetermined extent, a good voice quality is obtained. Since the sampling rate will not increase to unnecessarily high levels, power saving can be achieved and a consumption of batteries is reduced.

Abstract: A receiver of a radio frequency signal having a pseudo-random noise (PRN) code, and techniques of processing such a signal that are especially adapted for ranging applications. A signal corresponding to the PRN code is locally generated and used for decoding the received signal in a manner to reduce ranging errors that can result when multipath (delayed) versions of the radio frequency signal are also present. A significant application of the receiver and signal processing techniques of the present invention is in a Global Positioning System (GPS), wherein a number of such signals from several satellites are simultaneously received and processed in order to obtain information of the position, movement, or the like, of the receiver. A delay locked loop (DLL) correlator, provided in each of the receiver's multiple processing channels, locks onto a line of sight signal from one of the satellites with the effect of any multipath signal(s) being significantly reduced.

Abstract: According to the present invention, it is possible to improve a bit error rate performance of a conventional diversity receiver.In a diversity receiver of the present invention, first, second to Lth multiple differential detection signals and received signal strength are generated by multiple differential detection/signal strength detecting circuits, and are inputted into a combined branch metric generating circuit in a sequence estimator, thereby generating a combined branch metric. An ACS circuit is operated for an ACS operation on the basis of Viterbi algorithm by using the combined branch metric. A path memory sequentially takes as input path selecting signals outputted from the ACS circuit, and update the memory contents. A maximum likelihood state detecting circuit detects the most probable state by using a path metric outputted from the ACS circuit.

Abstract: A TDMA system receiver detects an offset amount of a carrier frequency of a received signal. A receiver for receiving a signal, including a periodic burst signal, includes a receiver unit for receiving a signal including a burst signal, a phase detecting circuit for detecting a phase of a predetermined pattern in a first burst signal and for detecting a phase of a predetermined pattern in a second burst signal, a calculating circuit for calculating an offset amount of a carrier frequency, and a correcting unit for correcting the offset amount of the carrier frequency.

Abstract: Correlation between a received signal and a PN code is obtained by a correlating portion. A correlation timing signal is detected by a correlation timing detecting portion, a delay profile is calculated by a delay profile calculating portion with reference to the correlation timing signal and a signal from a known data portion detecting portion. The delay profile is applied to a demodulating portion, and setting of path diversity is determined based on the delay profile.

Abstract: A decision feedback equalizer receiver that assigns a number F of feedforward filter taps and optimizes digital receiver performance in multipath channel environments, where F is an integer less than a memory length of a radio channel. The feedforward filter taps are assigned to delay times corresponding to an optimum burst timing parameter delay time, d(0), and to F-1 time delays based on "tap SNR indices." For an Uncorrelated Inter-Symbol-Interference (UISI) case, the F-1 time delays are the first F-1 rank ordered time delays are selected as the feedforward tap delay times. For a general case, a combination of the UISI case and an analytical two cluster case is obtained by selecting the first F-2 rank ordered time delays and a 2D time delay, where D is the delay time corresponding to the largest estimated tap SNR index.

Abstract: A system and method for communicating information signals using spread spectrum communication techniques. PN sequences are constructed that provide orthogonality between the users so that mutual interference will be reduced, allowing higher capacity and better link performance. With orthogonal PN codes, the cross-correlation is zero over a predetermined time interval, resulting in no interference between the orthogonal codes, provided only that the code time frames are time aligned with each other. In an exemplary embodiment, signals are communicated between a cell-site and mobile units using direct sequence spread spectrum communication signals. In the cell-to-mobile link, pilot, sync, paging and voice channels are defined. Information communicated on the cell-to-mobile link channels are, in general, encoded, interleaved, bi-phase shift key (BPSK) modulated with orthogonal covering of each BPSK symbol along with quadrature phase shift key (QPSK) spreading of the covered symbols.

Abstract: The wireless communication system transmits signals using radios (205). The radios (205) receive a signal which is formatted for transmission (602). The formatted signals from the radios (205) are divided. One formatted signal is input directly to a transform matrix (207) and a copy of the formatted signal is input to a delay (206) before being input to the transform matrix (207). Transform matrix (207) transforms (604) the input signals into output signals that each contain a portion of the input signals. The outputs from the transform matrix (207) are then amplified (605) using the amplifiers (208). The outputs from the amplifiers (208) are inverse transformed (606) in an inverse transform matrix (209). The inverse transform matrix (209) serves to recombine the portions of the signals originally input to the transform matrix (207). The resulting signals are then transmitted using antennas (210).

Abstract: A bus system providing increased connection flexibility and hot pluggable connections includes an open collector bus, a receiver connected to the open collector bus via a current sensor, a driver connected to the open collector bus, a peripheral card and a flexible cable operatively coupling the peripheral card, the receiver and the driver so as to provide point-to-point connection between the peripheral card and the open collector bus. The current sensor provides a control signal to the driver to increase the impedance of the driver in the event that a current is produced by the peripheral card.

Abstract: A testing apparatus for the digital processing portion of a satellite receiver. A software program generates an (I) and (Q) file of root cosine filtered (I) and (Q) DQPSK modulated sampled waveform. The waveform is coupled to a test board that stores the files in a PROM and generates the waveform at a rate determined by the receiver being tested. The output of the test board replaced the A/D converter of the receiver for testing. The waveform impairments are added to the stored software waveform.

Abstract: A spread spectrum communication method in which, on the transmission side, each item of parallel data is spread with a different code, and is encoded into a combination of I-channel and Q-channel signals. On the reception side, the combination of I-channel and Q-channel signals is encoded to correlate it with each of a plurality of codes.

Abstract: The invention concerns a method of controlling the minimal distance between successive errors in digital radio transmissions when multilevel modulations are used. With such a method the errors are spaced according to the needs, with an extremely reduced use of hardware with respect to prior art techniques. The method is characterized in that, in transmission a differential delay, i.e. different from flow to flow, is applied to each parallel flow not yet modulated, and in reception a differential delay is applied to each demodulated flow in such a way that the overall delay applied to each flow, i.e. the sum of the delay applied in transmission and the delay applied in reception, is constant and equal for all the flows.

Abstract: A method and circuit for generating an updated metric signal for an analog Viterbi detector is disclosed.