Abstract: A signal processor has an X-Y rotation circuit and a phase angle control circuit, in the phase angle control circuit, an input phase being approximated by a series of consecutive, in magnitude, decreasing phase angles for forming an output vector by rotation of an input vector over the approximation of the input phase. In the phase angle control circuit, an accuracy of the representation of a phase angle out of the series of phase angles, is dependent on the magnitude of the phase angle, thereby reducing the number of computations in the phase angle control circuit.

Abstract: Parallel digital data are transmitted along with a specific synchronization pattern added thereto. Each synchronization pattern adder adds the synchronization pattern at an equal timing for each channel. Parallel data after the synchronization pattern addition, are converted in parallel-to-serial converters into serial data which are in turn converted in an optical transmitter into optical signal. On the receiving side, the optical signal is converted in an optical receiver into an electric signal, from which the parallel data are restored in serial-to-parallel converters to be inputted to synchronization pattern detectors. The synchronization pattern detectors compare their shift register data and synchronization pattern and hold their synchronization pattern detection signal to be "1" for one time slot if the number of non-accord bits is within one. In the next time slot, a controller recognizes synchronization pattern detection when and only when all the synchronization pattern detection signals are "1".

Abstract: The present invention provides a matched filter which can refresh an entire while keeping the speed of a calculation comparable to a small sized circuit. The first and second addition circuits of a matched filter of the present invention are classified into a plurality of groups, the first and second auxiliary adders replace functions for the groups of the first and second adders respectively. The outputs of the first and second adders are then inputted to the first and second subtractors, respectively, and the refreshing means appropriately refreshes the groups replaced by the first and second auxiliary adders. Further, the present invention decreases the number of auxiliary sapling and holding circuits to be used, and decides the refreshing intervals by considering the change of the voltage caused by leakage and other permissible errors of output voltage.

Abstract: A data transfer device connected to a bus and a control signal line, includes: a judgment circuit for judging whether or not a state change of the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than the state change of the bus, which occurs in a case where data is output to the bus without manipulating the data; a first manipulation circuit for manipulating the data in accordance with the result of judgment; a first output circuit for selectively outputting one set of the data and the data manipulated by the first manipulation circuit to the bus in accordance with the result of judgment; and a second output circuit for outputting a control signal indicating the result of judgment to the control signal line.

Abstract: A communication system communicates a high-speed clock or other balanced signal on the backs of two data signals by differentially modulating the data signals with the clock signal and communicating the two data signals in differential common mode form. The clock signal is extracted from the data signals at the receiving end of the system by applying the data signals to differential line receivers.

Abstract: In a time diversity system (100) including a radio receiving device (110), a temporary address, a group message associated with the temporary address, and an instruction vector for activating the temporary address are transmitted as original information and, subsequently, duplicate information in a radio signal having frames of data. When the original instruction vector is not received by the receiving device (110), a later frame is searched for the duplicate instruction vector, which, when located, activates the temporary address stored by the receiving device (110). The receiving device (110) then determines which frame capable of reception by the receiving device (110) includes the group message, and the receiving device (110) searches for the temporary address and the group message in that frame. The temporary address is then deactivated.

Abstract: A method of determining a rate associated with a received signal including the steps of detecting the received signal (40); decoding the received signal at a first rate, determining a first path metric associated with the first rate, decoding the received signal at a second rate, and determining a second path metric associated with the second rate (44); calculating a plurality of discriminant functions based on the first and second path metrics (46); comparing at least one of the plurality of discriminant functions to a first predetermined value (48); and selecting one of the first and second rates as a determined rate based on the comparison.

Abstract: A data reception control device for receiving a group of commands transmitted by a start-stop transmission method including a first type of commands of which data transmission rates are detectable and a second type of commands of which data transmission rates are undetectable.

Abstract: In a dual CDMA mode and FM mode receiver, a local oscillator selectively outputs a local oscillation signal for a CDMA mode or a local oscillation signal for an FM mode in response to a command. A mixer mixes the local oscillation signal with an intermediate frequency signal to produce a signal having a predetermined frequency. Filters assigned to a CDMA mode and an FM mode, respectively, each filters the output of the mixer. After an AGC amplifier has amplified the output of the filter, a digital signal processor demodulates the output of the amplifier. Switches are provided for selecting either a CDMA mode or an FM mode.

Abstract: A method and apparatus for synchronization between a base station sub-system and a mobile station. The mobile station listens for a message frame number which is generated by the base station sub-system. The mobile station includes a mobile frame number counter which tracks the progression of frame numbers. When first powered-up, the mobile frame number counter may not be synchronized with the base station sub-system. The frame numbers of the base station sub-system and mobile frame number counter values are continuously incremented to track the progression of frame numbers in real-time. To effect synchronization, a received and decoded frame number is loaded into the counter. Then, a time lag is calculated which represents the delay inherent in receiving and decoding, within the mobile station and its components, frame numbers from the base-station sub-system.

Abstract: A subtraction device subtracts a predicted value generated by a predicting portion from a digital picture signal supplied through an input terminal. The subtraction device generates a difference signal as an output signal. A quantizing portion detects an activity of the difference signal, designates the number of quantizing steps corresponding to the activity, and quantizes the difference signal with the number of quantizing steps. The quantizing portion outputs side information to an output terminal.

Abstract: An adaptive digital data unit (600) initiates and successfully completes a remote loop back test. The adaptive digital data unit (600) has a controller (610), a local transmitter (620), a local receiver (640) a timer (622) and a detector (634). When a remote adaptive digital data unit (600) transmits a first data sequence and a second data sequence, the local adaptive digital data unit (600) receives the second data sequence from the remote digital data unit and determines if the second data sequence matches one of two predetermined data sequences. If so, a test successful flag is generated.

Abstract: The invention provides simple and reliable detection of .pi./4 shifted DQPSK modulated digital signals in a single-subscriber-unit, a multiple-subscriber unit (MSU) or a base transceiver station (BTS) of a fixed-wireless system, and is also directly applicable to other digital cellular or personal communication systems which utilizes a binary or M-ary PAM, FSK or PSK digital modulation scheme with differential or coherent encoding and time- and/or frequency-multiplexing. It offers great simplicity while providing soft-decision information for the later stage decoding of information bits encoded with an error correcting code. For each received sample z.sub.k+L and its estimated one z.sub.k+L, a Euclidean distance function is calculated. This Euclidean distance u(z.sub.k+L .vertline.v.sub.k+L, . . . , v.sub.k) is then added to the function derived from the previous iteration g(v.sub.k+L-1, . . . , v.sub.k), to yield a new Euclidean distance function f(v.sub.k+L, . . . , v.sub.k).

Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. The search is done in a linear fashion independent of the probability that a signal being searched for was transmitted at any given time.

Abstract: Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

Abstract: A communications device, such as a non-contact IC card, demodulates a received carrier signal, which has been modulated with data to be transmitted thereto by changing the phase of the carrier signal intermittently according to the data, so as to extract the data from the carrier signal.

Abstract: A differential signal receiver circuit includes a first differential stage receiving input differential signals, a second differential stage receiving shifted differential signals and summing stage summing outputs of the first and second differential stages. Preferably the summing stage is formed by a wired-OR connection between the first and second differential stage outputs. The circuit finds application in digital systems for receiving data transmitted between digital equipment.

Abstract: In a mobile radio system including mobile terminals each terminal comprises, on the receiving side, a unit using the Viterbi algorithm for equalization or for decoding the received signals after demodulation. A decision device of this system calculates the mean and the standard deviation of the metrics of each branch of the Viterbi algorithm, determines a quality level of a transmission parameter corresponding to the results of this calculation and compares the estimated quality level and a required quality level of the parameter in order to produce a decision signal supplied to a decision unit which can modify one or more transmission characteristics.

Abstract: A device is provided that interfaces with existing point of sale credit card reading devices, and furnishes the option of transmitting data over either the existing modem installation or a radio frequency data communication network. The device scans the information encoded on the credit card to determine which data transmission path is appropriate for a particular transaction. The device software generates the necessary signals to simulate the normal interaction between the POS cardreader device and a modem. The software also converts between serial and packetized data in order to request and receive credit card purchase authorizations over the radio frequency data communication network.

Abstract: A data recovery technique for jitter tolerant peak detected channels. The number of consecutive zeros between ones are reproduced in a run-length coded, peak detected channel. The interval (time, distance) is measured between peaks of a run-length encoded digital data signal wherein peaks represent ones and absence of peaks represent zeros. A look-up-table is provided having entries for all possible intervals between peaks for the run-length code used and corresponding entries for the number of zeros between ones. The measured interval is applied to the look-up-table to produce a string of zero bits between one bits.