Abstract: A frequency acquisition and compensation device and method for direct sequence spread spectrum communications systems has an identification (ID) sequence in an acquisition frame which is received by a receiving station and an ID sequence stored in an ID register. A received acquisition frame is demodulated using dot product and cross product demodulation. An ID detector detects the ID sequence in the demodulated dot product, cross product, or inverse cross product acquisition frame. When the ID is detected by the dot product demodulator, the receive frame timing is adjusted to coincide with a time interval when the ID was detected. Also, when the ID sequence stored in the ID register matches either the dot product, cross product or inverted cross product of the received ID sequence, the system microcontroller updates the automatic frequency control value.

Abstract: In a transversal filter for filtering an input signal (IN) into an output signal (OUT) in response to first through third tap gains (C.sub.-1, C.sub.0, C.sub.1), the transversal filter comprises a serial-parallel converter (40) for converting the input signal into first and second parallel converted signals. Connected to the serial-parallel converter, a delay circuit (10) has first through fourth taps (11-14) and comprises a plurality of delay units (16, 17) each of which is connected between two taps selected from the first through the fourth taps. Each of the delay units provides twice a unit delay which is substantially equal to a reciprocal of an input data rate of the input signal. The first through the fourth taps of the delay circuit produce first through fourth tap signals, respectively.

Abstract: Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.

Abstract: The present invention relates to a data communication system (12) which includes a receiver (14) capable of receiving serially transmitted signals and generates a receiver enabled signal and received data signal in response. A phase locked loop (16) generates a recovered clock signal in response to the received data signal and a first circuit (20) generates digitized data symbols in response to received data signals and the recovered clock signal. A nibble packetizer (28) forms data packets from the digitized data symbols and synchronizes transmission of the data packets in response to the receiver enabled signal, the digitized data symbols and the recovererd clock signal.

Abstract: An arrangement for monitoring a two-wire bus line for serial transmission of digital data includes a bus subscriber receiving circuit coupled to the two-wire line and including three comparators each having two inputs and an output for producing a logical output signal in dependence of signals at the two inputs. A signal line voltage on each wire of the two-wire bus line is applied, respectively, to the two inputs of a first one of the comparators and one of the two signal line voltages, an auxiliary voltage is applied, respectively, to the two inputs of a second one of the comparators and the other of the two signal line voltages and an auxiliary voltage being applied, respectively, to the two inputs of a third one of the comparators.

Abstract: A method and apparatus for synchronizing symbol timing for a QPSK demodulator. A matched filter pair outputs respective "early-punctual-late" signals. The early and late signals are input to a symbol synchronizing estimator that produces an interpolation control signal used by the filters to synchronize the symbol timing to the sample timing. The punctual signal is output as an information bearing signal representing the received inphase and quadrature signals. The matched filters are interpolating matched filters. The symbol synchronizing estimator normalizes the early and late signals in a manner that allow the demodulator to "flywheel" over signals having a low signal to noise ratio below a predetermined threshold.

Abstract: A method for providing adaptive modulation in a radio communication system employs a plurality of data modulation techniques (207). A two-way communication unit (100) automatically selects (318) from amongst the plurality of data modulation techniques (207), and uses the selected data modulation technique to transmit (308) data.

Abstract: A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable.

Abstract: A decimating digital PN receiver (10) processes a target return signal. The target return signal is decimated (34) processed at a slower speed. The decimated target return signal is then digitally correlated (28). The correlated signal is digitally filtered (30) and a fast Fourier transform (32) is applied to produce the output (33).

Abstract: A clock recovery circuit is coupled to an elastic storage circuit such as a FIFO circuit. More specifically, a first input of the elastic storage circuit is electrically connected to an output of the clock recovery circuit. A second input for accepts a data signal representing an input data stream from a communications medium. A third input accepts a local clock signal. The resultant circuit may be used in receiver's for communications systems to help alleviate the problems of frequency mismatch and jitter.

Abstract: A timing technique for a Quantization-Level-Sampling (QLS) modem puts timing information in a downstream pulsed signal transmitted from the public switched telephone network (PSTN) to the QLS modem. In response to this timing information, the QLS modem synchronizes to the network sampling clock of the PSTN. In particular, the pulsed signal includes data-bearing samples, which were provided by a far-end QLS modem, and at least one non-user-data-bearing (NUDB) sample in which the level of this NUDB sample periodically alternates. The QLS modem extracts timing information from this periodic alternating signal level to synchronize the QLS modem to the network sampling clock.

Abstract: In a communication system, digital data is convolutionally encoded and then differentially encoded before being phase shift key (PSK) modulated for transmission. An optimum process for coherent demodulation and soft-decision decoding of the data is disclosed. The received bit sequence through a Viterbi decoder is replaced with a differentially encoded version of the sequence, and a metric is computed. The path having the best metric of all possible paths is selected. The technique may be used not only for quadrature phase shift key (QPSK) modulated data but in general for any M-ary phase shift modulation. Further, an immunity to phase ambiguities caused by cycle slips is provided in the transmission and reception of data on fading channels through the combined convolutional and differential encoding of data.

Abstract: The object of the present invention is to provide a data transmission system, wherein even when more than two among a plurality of stations interconnected by one common transmission line try to communicate mutually by a start-stop transmission PWM mode, if the phases within a bit in the data of the own station and a corresponding bit of the data on the transmission line which has been received through a plurality of own station are compared and they coincide with each other as the result thereof, then the own station continues transmitting the data, while otherwise it comes to stop transmitting, whereby even if there is a difference between the clock frequency of the own station and that of another station, the phases in the corresponding bits of the two different data can be smoothly compared.

Abstract: A non-contact type IC-card with a simplified circuit arrangement which can select one of the PSK- and FSK-modulation methods at data transmission. A resonance frequency switching section is provided to halve the resonance frequency of a transmission and reception antenna. In the case of the PSK-modulation, the resonance frequency of the transmission and reception antenna is halved during one period of the original frequency at a modulation point so that the phase inverts for the phase modulation. In the case of the FSK-modulation, for the frequency modulation the frequency is switched over in accordance with the variation of the data. A PFSEL switch carries out the switching between both the modulation methods.

Abstract: A digital circuit is used to demodulate a linear chirp spread spectrum signal. The digital circuit uses a counter which is clocked so as to count during the time period between the pulses of a chirp signal. The circuitry also uses a digital filter to determine whether the frequencies of the linear chirp signal are within the correct bandwidth. The output of the counter is compared with the previous count to produce a difference count. A processor uses this difference count value to determine the characteristics of a chirp signal being decoded. A difference signal test circuit provides a digital filter for the difference count to eliminate spurious noise conditions.

Abstract: A self initialized coder and method thereof, the coder arranged and constructed for decoding an information stream, the coder including a buffer (301) for storing a portion (403) of the information stream, a controller (313) coupled to the buffer for temporally reversing a first part (401) of the portion to provide a file header (415), and an adaptive decoder (213) having a state parameter, the adaptive decoder, coupled to the controller and the buffer, for decoding the file header to provide an estimate of the state parameter and thereafter for decoding, using the estimate, the portion to provide a decoded signal.

Abstract: An automatic gain control apparatus of a spread spectrum signal receiver which can quickly follow distance variations, median variations, and instantaneous variations due to Rayleigh fading. An output of a variable gain amplifier 22 is quadrature-detected, the detected outputs are A/D converted, the digital output thereof are supplied to a despreading processor 34 through a digital level corrector 33, and the despreading output undergoes the instantaneous envelope detection by an instantaneous envelope detector 37. The envelope-detected signal is supplied to a symbol timing generator 38 which extracts data symbol timing component using a peak signal as a trigger, and a time window through which a desired signal enters is calculated from the symbol timing. Within the time window, the output of the instantaneous envelope detector 37 undergoes time integration by a level detector 43, and its output shifts the level of the digital level corrector 33, thereby making the output constant.

Abstract: An N-bit, byte-wise data randomizer uses a linear feedback shift register arrangement where each register stage stores N-bits. In this manner, a pseudorandom sequence can be generated based on a nonbinary primitive polynomial over a finite field of any desired length. In a specific disclosed embodiment, the primitive, degree three trinomialf(x)=x.sup.3 +x+.alpha..sup.3over the finite fieldF.sub.128 =F.sub.2 ?.alpha.!/(.alpha..sup.7 +.alpha..sup.3 +1)is implemented.

Abstract: A method is provided for detecting a synchronization word in frames of serially transmitted data. The synchronization word consists of l synchronization bits, which are transmitted one bit per frame at a known position in each frame. The method comprises the steps of: storing each incoming bit in a memory organized as groups of words, each having at least l bits, so that each group of words contains bits from a same position in consecutive frames; rotating each group of words; comparing the group of words, at each rotation, to the synchronization word.

Abstract: A method for digitally demodulating a complex modulation signal and allowing different parameters to be transmitted thereby. The input signal is baseband filtered and a complex demodulation is performed on the first subcarrier at a frequency Fp to obtain a correction signal, after squaring. The input signal is demodulated around a frequency exactly equal to twice the frequency of the first demodulation in order to obtain output signals which exhibit a frequency error with respect to 2Fp. This frequency error is corrected by multiplication with the previously derived frequency correction signal. The corrected signal is filtered at a frequency lower than 1 Hz, in order to obtain a signal giving the phase error at a frequency 0, that is to say that of the subcarrier at 2Fp. The signal makes it possible to correct the phase of signals which were previously frequency corrected in order to obtain two signals which are complementary to one another and transmitted by quadrature modulation around the frequency 2Fp.