Abstract: A method and apparatus for encoding and decoding QAM trellis modulated data. In the transmitter, a subset of bits of an input bit set are convolutionally encoded based upon a punctured convolutional code of a lower data rate to provide a set of coded symbols. The coded symbols and the uncoded bits of the input bit set are provided to a QAM modulator to provide a QAM modulation signal indicative of the values of coded symbols and the uncoded bits. In the receiver a QAM demodulator converts the received QAM signal to QAM signal space coordinates. A decoder employing the Viterbi algorithm is used to reconstruct a corrected estimate of the values of the coded data bits from the received signal coordinates. The corrected estimate of the values of the coded data bits are then used in conjunction with the received signal coordinates to provide corrected estimates of the values of the uncoded input bits.

Abstract: The present invention provides an apparatus and method for signal recovery from noisy observation in digital communication systems, utilizing a forward estimator and data smoother which improves the quality of the estimates of the transmitted signal. The present invention also provides an apparatus and method for the application of the forward estimator to the recovery of a digital data stream modulated with a CPM waveform, through the use of a receiver for GMSK demodulation. The digital data is first processed using the Forward Estimation process which calculates the probability that a symbol is in particular states. Bit decision is then applied, followed by scaling. The present invention further provides an apparatus and method for the application of the forward estimator and data smoother to the decoding of digital data which has been encoded with a Convolutional code. The digital data is first processed using the Forward Estimation procedure and then smoothed and scaled. Bit decision is then applied.

Abstract: A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18).

Abstract: A symbol generator (804) generates a time-domain discrete multi-tone symbol (810). A magnitude comparator (812) compares the magnitude of the time-domain discrete multi-tone symbol (810) with a magnitude threshold. When the magnitude of the time-domain discrete multi-tone symbol (810) compares unfavorably to the magnitude threshold, a magnitude adjusting symbol (816) is added to the time-domain discrete multi-tone symbol (810) such that the magnitude of the time-domain discrete multi-tone symbol (810) is reduced, thereby reducing the peak-to-average requirements (PAR).

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

Abstract: A 64 QAM signal constellation reduces phase noise as compared with a rectangular constellation, but requires a fairly simple decoder. The constellation has decision regions which are approximately rectangular; allows for quadrant decoding; and has constellation points representable by a small number of bits.

Abstract: To enable a serial data signal to be sampled reliably through a longer time period, the data signal is applied to a data slicer with a dynamically variable slice level. The slice level is dynamically adjusted in dependence upon a feedback of the sliced signal. A track-and-hold circuit, with control feedback from a low pass filter and peak detectors, provides for a design which is tolerant of timing variations. Also disclosed are circuits for reducing the effects of cochannel and other interferences.

Abstract: An adaptive equalizer is configured to reconstruct electronic signals which are transmitted over signal cables, such as twisted pair cables. The equalizer satisfactorily reconstructs the signals over a broad range of cable lengths. The degradation characteristics of a signal cable varies with cable length. Using the degradation characteristics for a cable over a desired range of lengths, the adaptive equalizer includes multiple parallel paths each of which are configured to reconstruct the input voltage signal optimized for a particular cable length. The degraded input signal is split according to a predetermined relationship into multiple partial signals, each signal for transmission through one each of the paths. Though each path is optimized to reconstruct the signal for a particular length of cable, the adaptive control adds a function of the actual cable length for more accurately reconstructing the signal. Each path forms a partial reconstructed signal.

Abstract: Digital data for generating a signal having a prescribed waveform is stored beforehand in the memory on the transmitting side of a communication system. The prescribed waveform is one obtained by combining signals having mutually different frequencies corresponding to the digits of a spread-spectrum code comprising a plurality of digits. When transmission data is inputted, the system generates, for every bit of data, a signal waveform corresponding to the value of the bit, based upon the data stored in the memory. The generated signal is a signal which has undergone spreading. This signal is placed upon a carrier wave and then sent to a transmission line. Like the transmitting side, the receiving side possesses digital data for generating a signal having a prescribed waveform. When a signal is received, the system generates a signal based upon the data possessed, multiplies this by the received signal and effects a conversion into a signal having an intermediate frequency.

Abstract: A clock system for a distributed multiprocessor system includes a plurality of local clock circuits and a distribution network. The distribution network includes a plurality of interconnected routers. Each local clock circuit is associated with a processing node of the multiprocessor system. Each local clock circuit generates a global clock source signal, provides the global clock source signal to the distribution network, receives a global clock signal back from the distribution network, and generates a global time value based on a local clock signal and the global clock signal. The router is part of the distribution network of the multiprocessor system. The router receives the global clock source signals from each of the local clock circuits, selects one of the global clock source signals as the global clock signal and provides the global clock signal to the distribution network for distribution to each of the local clock circuits.

Abstract: A phase shifter system includes a number of gates 40, 41 for receiving a reference clock and a number of gates 30-33 for receiving a predicted desired phase. The reference clock is manipulated by latches 43-46 and further gates 48, 49 so as to produce quadrature derivatives and these are connected across the resistor chain R1-R9 to produce multilevel waveforms, the steps being selected by selector 36 connected to the resistor nodes under the control of the predicted phase information from gates 30-33. Filtering and reshaping via comparator 50 provides an output clock pulse of desired phase. The output clock can be used to provide phase control in a transmission/reception system on a communications network.

Abstract: A method is provided of updating an estimated channel impulse response of a maximum likelihood sequence estimator within a radio receiver (12 and 13). The method includes the steps of computing a rate of change of a channel impulse response from a current estimated channel impulse response and a previous estimated channel impulse response, selecting an update step size as a function of the rate of change of the estimated channel impulse response, and updating the estimated channel impulse response of the maximum likelihood sequence estimator based upon the selected step size. Apparatus is also provided of practicing the method in receiving and decoding a signal.

Abstract: A high speed synchronous digital bidirectional data bus system is provided and includes an M-bit unterminated data bus, an unterminated standing sine wave clock bus, and a plurality of integrated circuit bus interfaces. Each IC bus interface is preferably substantially incorporated on a single CMOS LSI chip and includes M bus drivers with associated send data logic, M data receivers with associated receive data logic, and a clock receiver. The output currents of the bus drivers on all of the chips are preferably stabilized so that each driver drives the bus at substantially the same output current. The drivers are preferably complementary polar driven CMOS logic elements. For this case, for each data receiver, a bus keeper is coupled to the output and the input of the bus receiver to maintain the last state of the data bus. In addition, the clock receivers and the data receivers are embodied as high speed comparators having internal hysteresis.

Abstract: A receive processor device, in particular for a digital mobile radio system, includes a processor system comprising a set of functional units connected in cascade, some of which are decision units adapted to make decisions as to the value of information symbols that they receive. The decision unit is bypassed in the processor system and the value of information symbols to be processed by the next unit is deleted if the transmission quality of information symbols received by a decision unit is poor. Probable values for the deleted information symbols are determined from deleted information symbols and from undeleted information symbols received by the next unit.

Abstract: A detector of a carrier loss in a modem receiver of a fax transmission of a document, of the type includes a first calculator of the receive signal and a first comparator of this energy with respect to a threshold. The detector further includes means for adapting said threshold between each page of the transmitted document.

Abstract: A synchronization apparatus in a selective call receiver comprised of a digital variable bandwidth phase locked loop with means to simultaneously detect the synchronization code word, means to generate a binary code from a register representative of lock quality, means to increment or decrement the lock quality register, means to sum the lock quality binary code into a phase error register, whereby the polarity of the sum is controlled by a phase comparison of the a local clock with the received data, and whereby the under or over flow of the phase error register determines the direction of a phase adjustment to the local bit clock generator.

Abstract: A system for adaptively determining a bitwise weighting factor for coded binary data comprising a correction unit that provides an overall weighting factor representative of the sum of the products of the individual symbol probability factor times the bit value.

Abstract: The invention provides a transmission timing measuring apparatus for accurately measuring the transmission timing between channels of a base station and a mobile station in, e.g., a system using a digital time-division modulation scheme in which the base station and the mobile station perform communication using different frequencies. In the transmission timing measuring apparatus of the invention, reference and measurement channel signals having different frequencies are converted into digital data by a signal processing section (20) and are selectively output. A data write section (6) temporarily stores each data in a pre-assigned memory area in a memory section (15) by using an accurate clock. A data read section (7) reads out each data from the memory area on the basis of the reference channel. A transmission timing calculating section (10) calculates the transmission timing from the time difference between symbol sequence data read out from the memory section (15).

Abstract: A digitally modulated signal is conditioned, such as to facilitate amplification. The digitally modulated signal is derived from an information stream which is mapped onto a symbol constellation to generate a sequence of channel symbols. The sequence of channel symbols is processed to provide a conditioned signal having a signal envelope that avoids signal envelope magnitudes below a threshold value (500). From a signal envelope representing the sequence of channel symbols, symbol interval minimum values are determined as the signal envelope transitions through successive channel symbols of the sequence (510). The conditioned signal is generated by localized adjustment of the signal envelope, such as by insertion of an adjustment pulse, to increase a particular symbol interval minimum value, when that value is below the threshold value (520, 530, 540, 545, 555).

Abstract: A phase-lock loop circuit with fuzzy control, includes a phase comparator whose output is connected to a low-pass filter that drives a voltage-controlled oscillator. The phase comparator generates a signal that represents the phase difference between an input signal and a signal generated by the oscillator. The oscillator of the present invention is furthermore driven by a control signal generated by fuzzy control. The input of the fuzzy control is the signal that represents the phase difference.