Patents Examined by C. Chaudhari
  • Patent number: 5418174
    Abstract: A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: May 23, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Alexander Kalnitsky
  • Patent number: 5416039
    Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: May 16, 1995
    Assignee: Siliconix Incorporated
    Inventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun W. Chen
  • Patent number: 5407849
    Abstract: A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: April 18, 1995
    Assignee: IMP, Inc.
    Inventors: Moiz Khambaty, Corey D. Petersen
  • Patent number: 5401686
    Abstract: The temperature of the front heater is set to a higher value than the set temperature of the center heater and the temperature of the rear heater is set to a lower value than the set temperature of the center heater to thereby provide such a temperature gradient that the temperature of a center heater region gradually rises from the rear side toward the front side and the impurity diffusion is accelerated under the temperature gradient, whereby it is possible to compensate for the decrease in the quantity of the diffused impurity caused by the lowering of the impurity concentration of the impurity gas gradually from the rear side toward the front side, so that the impurity is uniformly diffused into the wafers located in the core pipe.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: March 28, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Hiromi Kiyose
  • Patent number: 5399525
    Abstract: A method for the manufacture of integrated circuits where it is desired to produce narrow conducting grids separated by a narrow gap and uses the lifting-up of silicon nitride (bird's bill) which is formed during a thick localized oxidation. A localized oxidation step is carried out and the oxide formed is totally removed. The edges (20, 22) of a nitride layer (14) stay overhanging. A conforming polycrystalline-silicon deposition enables silicon to be deposited uniformly, including beneath these edges. Finally, vertical anisotropic etching removes the silicon everywhere except beneath the overhanging edges, so that two silicon lines (28, 30) remain. An ion implantation (34) may be performed between the two lines. The method will find particular application for making anti-dazzle systems for photosensitive charge-coupled devices.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: March 21, 1995
    Assignee: Thomson-CSF Semiconducteurs Specifiques
    Inventor: Pierre Blanchard
  • Patent number: 5395804
    Abstract: A method for fabricating a thin film transistor formed on an insulator is disclosed. The method includes the steps of forming a non-single crystal silicon film on the insulator, forming a polysilicon film on the insulator by thermally treating the non-single crystal silicon film in an atmosphere of a gas including hydrogen halogenide, and forming a channel region in the polysilicon film.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: March 7, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tohru Ueda
  • Patent number: 5393684
    Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: February 28, 1995
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Paolo Ghezzi, Federico Pio, Carlo Riva
  • Patent number: 5391505
    Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: February 21, 1995
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5384280
    Abstract: A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer. The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: January 24, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masami Aoki, Hiroshi Takato
  • Patent number: 5362660
    Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: November 8, 1994
    Assignee: General Electric Company
    Inventors: Robert F. Kwasnick, George E. Possin, David E. Holden, Richard J. Saia
  • Patent number: 5350704
    Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: September 27, 1994
    Assignee: TRW Inc.
    Inventors: James M. Anderson, Andrew R. Coulson, Vincent J. Demaioribus, Henry T. Nicholas
  • Patent number: 5348897
    Abstract: Transistor fabrication methods are provided which are suitable, for example, for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment in which the channel region overlies the gate, a first mask is formed over the channel region, and then an LDD implant is carried out. A second mask is then formed over the LDD portion of the drain region. The second mask is allowed to extend over the first mask. A heavy doping implant is then carried out. Thus an LDD structure can be provided on the drain side but not on the source side with only one mask--the first mask--defining the channel length. In some embodiments, both masks include photoresist. The first photoresist mask is hardened to prevent its lifting during development of the resist of the second mask.
    Type: Grant
    Filed: December 1, 1992
    Date of Patent: September 20, 1994
    Assignee: Paradigm Technology, Inc.
    Inventor: Ting-Pwu Yen
  • Patent number: 5340772
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Patent number: 5340770
    Abstract: A shallow junction spin on glass (SOG) process which provides shallow junction semiconductor devices without defects and leaky junctions. The process includes spinning first and second SOG layers containing first and second dopants onto a semiconductor substrate and diffusing the dopants into the substrate to form first and second junctions. The diffusion time and temperature are controlled so as to produce junctions having depths less than a predetermined maximum depth. Insulating and metal interconnect layers are deposited on top of the SOG layers. The insulating layer may include boron-phosphorus silicon glass (BPSG).
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: August 23, 1994
    Assignee: NCR Corporation
    Inventors: Derryl D. J. Allman, Dim-Lee Kwong
  • Patent number: 5332681
    Abstract: The present invention provides a method for depositing a pattern of deposd material on or within a substrate, comprising the steps of: interposing a glass mask between a source and a substrate, the mask having channels therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate. The present invention also provides semiconductor devices made by this method.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: July 26, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ronald J. Tonucci, Brian L. Justus
  • Patent number: 5330614
    Abstract: Disclosed are a semiconductor memory device and method for manufacturing the same. The method includes a process for manufacturing a capacitor performed by the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern composed of a 1st first-material layer on the first conductive layer, forming a first sidewall spacer composed of 1st second-material layer on the resultant structure, and etching the material layer under the first sidewall spacer, using the first sidewall spacer as an etch-mask. The semiconductor memory device thus manufactured can be highly integrated and is highly reliable.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: July 19, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-hong Ahn
  • Patent number: 5322813
    Abstract: A CVD process for producing a rare earth-doped, epitaxial semiconductor layer on a substrate is disclosed. The process utilizes a silane or germane and a rare earth compound in the gas phase. By this method single phase, rare earth-doped semiconductor layers, supersaturated in the rare earth, are produced. The preferred rare earth is erbium and the preferred precursors for depositing erbium by CVD are erbium hexafluoroacetylacetonate, acetylacetonate, tetramethylheptanedionate and flurooctanedionate. The process may be used to produce optoelectronic devices comprising a silicon substrate and an erbium-doped epitaxial silicon film.
    Type: Grant
    Filed: August 31, 1992
    Date of Patent: June 21, 1994
    Assignee: International Business Machines Corporation
    Inventor: David B. Beach
  • Patent number: 5316969
    Abstract: Shallow regions are formed in a semiconductor body by irradiating the surface region with a pulsed laser beam in an atmosphere including the dopant. The pulsed laser beam has sufficient intensity to drive in dopant atoms from the atmosphere but insufficient intensity to melt the semiconductor material. A silicide layer can be placed over the surface of the semiconductor material prior to irradiation with the dopant being driven from the atmosphere through the silicide into the surface region of the semiconductor body. Alternatively, the silicide layer can include dopant atoms prior to irradiating the surface region.
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: May 31, 1994
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Emi Ishida, Thomas W. Sigmon, William T. Lynch
  • Patent number: 5310698
    Abstract: In a multistage process for producing a smooth polycrystalline silicon layer, in particular a layer with low arsenic doping, for very large scale integrated circuits, by thermal decomposition of gaseous compounds containing the elements, a doped layer and an undoped silicon layer above the doped layer are deposited directly one after the other in a two-stage process. Initially, a surface-covering arsenic layer being at most a few atoms thick, is deposited as a preliminary lining. Then an undoped amorphous silicon layer is deposited on the arsenic layer at a temperature of less than C. Subsequently, the silicon layer is uniformly doped with the arsenic layer serving as a diffusion source, by temperature treatment. Simultaneously, the amorphous silicon is made into a polycrystalline silicon layer.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: May 10, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventor: Barbara Wild
  • Patent number: 5308440
    Abstract: A semiconductor device with air-bridge interconnection comprises: a substrate; a plurality of mesas with distance therebetween smaller than a predetermined value; and a metal layer supported by the plurality of mesas, the metal layer having a narrow portion at the intermediate portion thereof and both ends having larger width than the narrow portion. The air-bridge interconnection is obtained by side-etching controlled during dry-etching using interconnection metal layer as an etching-mask to remove a mass of semiconductor material under the interconnection metal layer.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: May 3, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoji Chino, Kenichi Matsuda, Jun Shibata