Abstract: For manufacturing an implantation mask on a semiconductor surface which is provided with grooves, a positive photoresist is provided on the surface. Portions of the photoresist which are to form the implantation mask are illuminated in a first step and rendered insoluble in the developer in an image reversal step. The photoresist is then illuminated without mask and developed, so that the portions not illuminated during the first step are removed. The implantation mask thus obtained has a receding profile, the openings at the area of the grooves becoming wider in the direction of the bottom of the grooves.

Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.

Abstract: A charge coupled device (CCD) has a single level electrode of single crystalline silicon on an insulating layer over a surface of a body of single crystalline silicon. The CCD is made by forming a layer of insulating material on a surface of a body of single crystalline silicon with a portion of the surface being exposed. A layer of single crystalline silicon is then epitaxially grown by epitaxial lateral overgrowth on the exposed surface of the body and over the insulating material layer. The layer of single crystalline silicon is removed from the surface of the body to insulate the single crystalline silicon layer from the body by the insulating material layer. Portions of the layer of single crystalline silicon are removed to form a plurality of separate gate electrodes.

Abstract: A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A second region (22) of the masking layer (14) is etched to form a single opening or a second plurality of openings different in geometry from the first plurality of openings. A single ion implant step or an equivalent doping step is used to dope exposed portions of the substrate (12). The geometric differences in the masking layer (14) between region (20) and region (22) results in the formation of the first and second doped regions (24 and 26) wherein the first and second doped regions (24 and 26) vary in doping uniformity, doping concentration, and doping junction depth.

Abstract: A semiconductor device provided with an external connection terminal composed of a metal bump electrode. A first metal film is formed on the entire surface of the semiconductor device, a second metal film on the first metal film, and a third metal film on the second metal film. A resist film is selectively formed on the third metal film. A metal bump electrode is formed on the third metal film, at a portion at which the resist film is not present by electrolytic plating while using the third metal film as a conductive plating electrode and the resist film as a mask. The resist film is removed and the metal films are etched while using the metal bump electrode as a mask.

Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Abstract: The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.

Abstract: A fabrication method for a microstructure having a vacuum sealed cavity therein including the process steps of forming an aluminum filled cavity in a body of silicon material and heating the structure such that the aluminum is absorbed into the silicon material leaving a vacuum in the cavity. In one embodiment of the invention a cavity is etched into a silicon wafer and filled with aluminum. A silicon dioxide layer is formed over the aluminum filled cavity and the structure is heated to produce the vacuum cavity.

Abstract: In a method of manufacturing CMOS transistors, a well that is of a second conductivity type is formed in a semiconductor substrate of a first conductivity type and is surrounded by a high concentration buried layer of the first conductivity type which completely extends around and below the well, and which also constitutes wells of the first conductivity type. The high-concentration buried layer is formed by a self-aligned process, and the potential of the buried layer can be easily fixed from the top of the semiconductor substrate so that a high degree of resistance is obtained to CMOS latch-up.

Abstract: A method of making a two-phase charge coupled device (CCD) includes forming a layer of a conductive material over and insulated from the surface of a body of a semiconductor material of one conductivity type having a channel region of the opposite conductivity type in the body and extending to the surface. Sections of a first masking layer are formed on the conductive material layer spaced along the channel region. A conductivity modifying dopant is implanted into the channel region through the spaces between the sections of the first masking layer. A layer of a second masking layer is formed over the sections of the first masking layer and on the surface of the conductive material layer in the spaces between the sections of the first masking layer. A layer of indium-tin oxide (ITO) is formed over the portions of the second masking layer which extend across the ends of the sections of the first masking layer, and a layer of carbon is formed on the second masking layer between the ITO layers.

Abstract: Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopants to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Abstract: A lower electrode of a stacked capacitor in accordance with the present invention is formed of a silicon layer formed by low pressure CVD method. The silicon layer is formed by thermal decomposition of monosilane gas at a prescribed temperature. By setting partial pressure of the monosilane gas and formation temperature at prescribed values, the silicon layer is formed to be in a transitional state between poly crystal and amorphous. Such silicon layer has large concaves and convexes on the surface thereof. Consequently, opposing areas of the electrodes of the capacitor can be increased, and therefore electrostatic capacitance of the capacitor is also increased.

Abstract: A photoresist mask composed of a plurality of isolated plane patterns having no opening is formed on a main surface of a semiconductor substrate. The breakdown of the gate oxide film due to charge build up can be prevented because no photoresist mask opening patterning is involved.

Abstract: This invention is directed to a process for the fabrication of a stacked semiconductor nonvolatile memory device, which process is adapted to define a longitudinal length of a floating gate in self-alignment with overlying control gate and interlayer insulating film by etching, without severely damaging the underlying semiconductor substrate.

Abstract: The invention relates to a solid-state imaging device in which a light-sensitive element region and a charge transfer region are separately formed on a semiconductor substrate of a first conductivity type by implanting an impurity of a second conductivity type into the substrate. A channel region is formed between these two regions by implanting an impurity of the first conductivity type into the substrate. Next, charge transfer electrodes made of a light-proof material are formed on the light-sensitive element region and the charge transfer region, with insulating films thereunder.An alloy of a high-melting-point metal and silicon is used in the construction of the charge transfer electrodes, and this alloy is subjected to high-temperature processing in an atmosphere of O.sub.2.

Abstract: A process for spatially controlling the etching of a silicon substrate by omic hydrogen. The process may be generally carried out at room temperature. The process involves implanting a boron dopant in selective portions of the silicon substrate followed by etching with atomic hydrogen. The implanted portions exhibit no etching by atomic hydrogen. A silicon device that is produced by this process is disclosed.

Abstract: A method of processing a semiconductor device in which a microwave field is generated to surround the semiconductor device while a focussed electron beam or ion beam is applied to the substrate of the device whereby the presence of the electron or ion beam creates a conductive region which increases the microwave field intensity in that region, so that the intensified microwave field creates a local heating effect in the substrate to perform a local annealing action.

Abstract: According to this invention, an oxide film is formed on a semiconductor substrate, a metallic boron film or a film containing at least one selected from the group consisting of boron, phosphorus, and arsenic is deposited on the surface of the resultant structure. At least one selected from the group consisting of boron, phosphorus, and arsenic is doped from the metallic boron film or the film containing at least one selected from the group consisting of boron, phosphorus, and arsenic to the oxide film by diffusion without diffusing into the semiconductor substrate. Thus, a semiconductor device having good radiation resistance can be obtained.

Abstract: The present invention is intended to provide a method of fabricating an EEPROM having excellent endurance characteristics. A work obtained by processing a substrate (1) by a wafer processing process including a passivating process and having a tunnel oxide film, an aluminum wiring film and a passivation film is subjected to a low-temperature heat treatment employing a processing temperature of about 250.degree. C. and a processing time on the order of 50 hr in a thermostatic oven (20) in the presence of nitrogen gas. The low-temperature heat treatment reduces trap sites produced in the tunnel oxide film by a plasma CVD process carried out to form the passivation film to repair the tunnel oxide film damaged by the plasma CVD process and to improve the endurance characteristics. The aluminum wiring film is not deteriorated by the low-temperature heat treatment because the low-temperature heat treatment employs a relatively low processing temperature.

Abstract: A process, compatible with bipolar and CMOS silicon device manufacturing for fabricating complementary buried doped regions in a silicon substrate. An N+ doped region (12) is formed in the silicon substrate by known methods of arsenic doping and drive in. This is followed by depositing a first thin epitaxial silicon cap layer (14), under conditions of minimum N+ autodoping. Part thickness of this first epilayer is converted to oxide (18), and the oxide is patterned to provide apertures in an area where it is desired to form a P+ region. A P source material (20) is deposited and a drive in anneal is used to dope the silicon with P in the areas of the oxide aperture opening. Subsequent to drive in, the dopant source layer and the oxide mask is removed by wet etching. An oxide is regrown on the surface, including the P+ region (22), and subsequently the oxide layer is stripped in dilute hydrofluoric acid.