Abstract: A method of manufacturing a semiconductor device includes the steps of: forming a gate electrode and a wiring layer on a silicon oxide film formed on the surface of a semiconductor substrate, by using conductive material; forming a diffusion region on the surface of the semiconductor substrate by implanting impurities into the semiconductor substrate at an area other than the gate electrode and the wiring layer; and forming a film for electrically interconnecting the diffusion region and the wiring layer, using conductive material.

Abstract: A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type.

Abstract: A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentration. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall.

Abstract: A method of forming a silicon-germanium epitaxial layer using dichlorosilane as a silicon source gas. A semiconductor seed layer (15) is formed on a portion of a semiconductor layer (12) and on a portion of a layer of dielectric material (13). The semiconductor seed layer (15) provides nucleation sites for a Si-Ge epitaxial alloy layer (16). The epitaxial film (16) is formed on the semiconductor seed layer (15). Both the semiconductor seed layer (15) and the Si-Ge epitaxial film (16) are formed at a system growth pressure between approximately 25 and 760 millimeters of mercury and a temperature below approximately 900.degree. C. The semiconductor seed layer (15) and the Si-Ge epitaxial film (16) permit fabrication of a heterostructure semiconductor integrated circuit (10), thereby allowing the exploitation of band-gap engineering techniques.

Abstract: Problems arise when connecting the bottom plate of a ferroelectric capacitor to the source of its associated access transistor during the fabrication of an ultra large scale integrated memory circuit. The temperature and ambient of certain steps of the fabrication process adversely affects ohmic properties of the connection. To overcome these problems, an insulative layer is formed between the bottom plate of a ferroelectric capacitor and its associated transistor. The insulative layer separates the source from the bottom electrode, and subsequent high temperature swings during the remainder of the fabrication process do not produce any direct connection between the source and the bottom plate. After the memory circuits have been fabricated on the semiconductor wafer, a voltage is applied across the ferroelectric capacitor and the insulative layer, preferably during a wafer probe. The magnitude of the applied voltage is selected to breakdown the insulative layer, but does not damage the ferroelectric layer.

Abstract: A process for increasing the minority carrier recombination lifetime in a silicon body contaminated with transition metals, expecially iron. The silicon body is stored at a temperature and for a period sufficient to cause metal to diffuse from the bulk of the silicon body to the surface of the silicon body to measurably increase the minority carrier recombination lifetime.

Abstract: An improved method for fabrication of a super-high density semiconductor device wherein ion implantation is used to eliminate defects or inhibit the occurrence of growth of defects in the semiconductor device. Ions of high concentration are implanted into a monocrystal semiconductor region in which principal elements such as bipolar element and MOS element are formed, by using a mask pattern covering the semiconductor region and at a largely inclined implantation angle equal to or of more than 20 degrees. This provides for formation of amorphous regions 170A, 170B extending sufficiently into areas beneath the ends of the mask. The amorphous regions are recrystallized by heat treatment, thereby inhibiting the growth of a corner defect known as "voids 21" which has often occurred at edges of amorphous regions 170A, 170B in the conventional method. Thus, a device which is less liable to electrical leaks is provided.

Abstract: The present invention discloses an incoherent radiation regulated voltage programmable link circuit and a method for making the circuit. The voltage programmable link circuit lowers the programming voltage of the link to that of the normal operating voltage by applying electromagnetic radiation to the link structure. The radiation may be radio frequency radiation, or ultraviolet radiation may be applied through a transparent conductive element.

Abstract: A fabrication process of a semiconductor device comprises the steps of providing a temporary layer on a semiconductor substrate, patterning the temporary layer to form a temporary protection pattern on the semiconductor substrate such that the temporary protection pattern has a pair of opposing side walls extending generally vertically, relatively to the semiconductor substrate, forming a first conductor layer, having incorporated therein an impurity element of a first conductivity type, so as to bury the temporary protection pattern therebeneath, patterning the first conductor layer to form a pair of first type conductor regions contiguous the respective, opposing side walls of the temporary protection pattern, removing the temporary protection pattern selectively with respect to the first type conductor regions thereby to leave the pair of first type conductor regions on the substrate, forming a second conductor layer such that the second conductor layer buries the first type conductor regions therebeneath,

Abstract: A method for manufacturing mask ROMs is disclosed, wherein a semiconductor substrate of a first conductive type, on which a gate insulating layer, a poly-silicon layer, source and drain regions and a spacer are formed is stored after depositing the entire surface of the structure with a protection layer until the next steps such as programming, so that the poly-silicon gate and the source and drain regions of the structure can be prevented from being polluted with organisms or matriums, etc. by forming a protection layer before the storage, thereby improving the efficiency and reliability of mask ROMs, and the ROM data region can be checked during the etching of the protecting layer for distinguishing the defective chips simply and efficiently in a short manufacturing time.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.

Abstract: A first semiconductor substrate comprises an integrated circuit formed therein and an alignment mark formed thereon. The top surface of the first semiconductor substrate is covered with a first insulating layer and is planarized. The alignment mark is formed in a space between a plurality of groups of elements, such as a scribe line area. A second semiconductor substrate is provided with a groove corresponding to said space, or scribe line area, and a second insulating layer is formed on thereon and so as to bury the groove, and the exposed surface of the second insulating layer is planarized. The two planarized surfaces of the first and second semiconductor substrates are positioned in facing, contiguous relationship and are bonded to each other, while an infra-red microscope is used for alignment of the space and the groove. The back surface of the second semiconductor substrate is selectively etched until the second insulating layer, as filed in the groove, is exposed.

Abstract: Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi.sub.2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi.sub.2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.

Abstract: A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semiconductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.

Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.

Abstract: In a method for producing a II-VI compound semiconductor device including mercury, a thin film of a group II element or a group II element compound, which is a solid at room temperature, is deposited on a surface of a p type II-VI compound semiconductor. Annealing is carried out to diffuse the group II element from the thin film into the p type II-VI compound semiconductor whereby a region of the p type II-VI compound semiconductor on which the thin film is present is converted to n type, resulting in a p-n junction. Therefore, instruments and materials are easily handled, increasing work efficiency and productivity. In addition, the annealing is carried out without a complicated temperature profile, resulting in a simple process.

Abstract: A blanking aperture array for use in a charged particle beam exposure has a substrate, at least m rows by n columns of apertures arranged two-dimensionally in the substrate, where each of the apertures have a pair of blanking electrodes and m and n are integers greater than one, and n m-bit shift registers provided on the substrate for applying voltages dependent on pattern data to m pairs of the blanking electrodes of the apertures in the ith column, where i=1, 2, . . . , n. The pattern data is related to a pattern which is to be exposed using the blanking aperture array.