Abstract: After an interlayer insulator film is deposited on a wiring conductor formed on a semiconductor device element and is then planarized, a first conducting film and a first insulating film are deposited in the named order. Thereafter, a through hole is formed, and a second conducting film and a second insulating film are deposited and then etched back so that these films remain on only a side wall surface of the through hole. Furthermore, the through hole is filled with a metal plating, and then, the etching-back is performed again. Thereafter, an upper level wiring conductor is plating-grown by supplying an electric current to-the first conducting film , and the second conducting film remaining on the side wall surface and the lower level wiring conductor.

Abstract: There is disclosed a method for forming a contact in a semiconductor device wherein a contact material is contacted with an area of a first conductive film between second conductive film patterns which are insulated with the first conductive film and closely adjacent to each other. The method comprises the steps of contacting with the first conductive film a first contact mediator passing by the second conductive film patterns, in a self-alignment manner, contacting a second contact mediator with a predetermined area of the first contact mediator, forming a conductive film spacer at a side wall of the second contact mediator with the contact mediator being patterned, and forming the contact material on the contact mediator.

Abstract: N-type c-BN is a heat-resistant material with a wide band gap. Ohmic electrodes are indispensable for making semiconductor devices utilizing n-type c-BN. The electrodes proposed so far are likely to deteriorate in an atmosphere of high temperature. The degradation of electrodes hinders the production of semiconductor devices utilizing c-BN. A heat-resistant ohmic electrode is produced by forming a low contact resistance layer of a boride or a nitride of Ti, Zr or Hf on a heated c-BN and by covering the low resistance layer by an Au layer. Otherwise an ohmic electrode is produced by forming a low contact resistance layer of one of Ti, Zr, Hf, etc. on c-BN, making a diffusion barrier layer of W, Mo, Ta or Pt and depositing an Au layer on the diffusion barrier layer.

Abstract: An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on.

Abstract: A first Al wire is connected to a gate electrode. On the first Al wire, an insulating film is provided. In the insulating film, an opening with a large cross-sectional area is made so as to correspond to the first Al wire. In the periphery of the opening, the insulating film is etched by RIE to make an opening. In the central area, the insulating film is etched by wet etching to make an opening. Inside the opening thus made, a second Al wire is formed. The second Al wire is connected to the first Al wire inside the opening. When the opening is made, the number of electrons trapped in the gate oxide film is small because the area etched by RIE is small. Since RIE etches the first Al wire deeper than wet etching, recesses are made around the first Al wire located inside the opening. The first and second Al wires are connected to each other via the recesses.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a wiring layer on the surface of a semiconductor substrate, depositing a silicone film on the whole surface of the semiconductor substrate including the wiring layer by a CVD method and exposing the silicone film to oxidative plasma with enhanced frequencies including components of 1 MHz or less to change to a silicon oxide film, the depositing step and exposing step being alternately repeated in the same apparatus till the silicon oxide film having any desired thickness is obtained. The resulting silicon oxide film has the smooth surface and the high density.

Abstract: A new method of metallization without unwanted precipitates using a tungsten plug is achieved. Semiconductor device structures are formed in and on a semiconductor substrate. A contact hole is opened through an insulating layer to the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A layer of tungsten is blanket deposited over the glue layer. The tungsten layer is etched back leaving the tungsten only within the contact opening to form a tungsten plug. The etching back leaves impurities on the surface of the glue layer. Those impurities will react with water or air to form precipitates. The precipitates are removed using a wet chemical etch. The substrate is post treated with argon ion sputtering to prevent future formation of precipitates.

Abstract: Conductors are fabricated by forming a layer of doped polysilicon on a semiconductor substrate, forming a nitrogen-enriched conductive layer on the layer of doped polysilicon, wherein nitrogen contained in the nitrogen-enriched conductive layer provides for improved thermal stability thereof, and patterning the nitrogen-enriched conductive layer and layer of doped polysilicon so as to form the conductors.

Abstract: In order to fill contact holes (43) formed in an isolation layer (41) laid on a semiconductor substrate (13) and having a principal surface and sidewalls defining the contact holes with aluminum of a covering material which is sputter deposited in a sputter chamber to lay a covering film (47) on the principal surface and on the sidewalls, the covering film is brought into contact with an inert gas atmosphere in a reflow chamber and is subjected to irradiation by plasma of inert gas ions for removal of an aluminium oxide film (49) undesiredly formed on the covering film and, either subsequently by application of heat to the substrate or simultaneously by the irradiation, for reflow of aluminium of the covering material into the contact holes to provide a conductor film (51) covering the principal surface and filling the contact holes. Preferably, the plasma is given small ion energy of 30 to 50 eV and a high ion density.

Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C.

Abstract: A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which con

Abstract: After forming lower level wiring and plasma oxide layer, SOG film is applied by applying a solution containing hydrogen silsesquioxane as primary component under rotation. Pre-baking of the SOG film is performed by a first heat treatment and causes reflow thereof by a second heat treatment at a temperature higher than the first heat treatment. Subsequently, another plasma oxide layer is formed. By this, in an interlayer insulation layer including SOG film, occurrence of crack and so forth can be prevented and water resistance can be improved.

Abstract: A method of processing an insulating film containing voids associated with the increased semiconductor device density is performed. An insulating film containing voids is coated with another insulating film by spin-on technique to substantially close up the voids, followed by photolithography process. By the processing without adverse affects from the presence of voids, for example, an undamaged cover film can formed, which can contribute to greater reliability of semiconductor devices.

Abstract: A method for making a self-aligned oxide gate cap is provided. The method requires only one photoresist step to make a self-aligned oxide cap that can serve as an implant block and provide self-aligned contacts. A substrate with a gate line is provided. A first oxide layer (36) is then isotropically deposited over the gate line. A portion of the first oxide layer (36) is then etched anisotropically. A second oxide layer (40) is then isotropically deposited over the gate line and the remaining first oxide layer (36). A spacer mask (43) is then formed over the gate line. If preferred, the spacer mask (43) could be extended beyond the spacer region to further separate the drain region from the gate line with dielectric creating a lightly doped drain region. The exposed oxide layer is etched anisotropically, resulting in a dual-step spacer (44) that can act as an implant mask for the source and drain regions and as a self aligned ohmic contact area.

Abstract: A structure and method is provided for forming a contact plug in a contact hole in a dielectric layer on a semiconductor substrate. A polysilicon spacer is formed on the sidewalls and bottom of the contact hole. A metal, such as titanium, is deposited on the sidewalls and bottom of the hole and on the dielectric layer. The substrate is heated to form a metal silicide layer, such as TiSi.sub.x, and a metal nitride layer, such as TiN, on the side-walls and bottom of the contact hole. Any remaining metal layer and metal nitride layer formed in the heating process is removed. This leaves the titanium silicide layer on the contact hole walls. Tungsten is deposited to fill the contact hole where the metal silicide promotes the nucleation of the tungsten. In a preferred embodiment, to further promote nucleation of the tungsten, a second metal nitride layer is formed on the surface; of the metal silicide layer just prior to tungsten deposition.

Abstract: A production method of a semiconductor device which has a first insulator film formed directly or through at least one layer on a semiconductor substrate, a wiring film containing gold (Au) and formed on the first insulator film, a metal layer covering the surface of the wiring film, and a second insulator film formed on the metal layer to cover its surface. The metal layer is made through an absorption process or phenomenon of a metal included in the metal layer. Preferably, the metal layer is made of tungsten (W) or molybdenum (Mo) and the wiring film is made of a gold (Au) layer and at least one electroconductive layer stacked. An improved adhesion between the wiring layer and an insulator film formed thereon can be obtained.

Abstract: A method of forming a local interconnect for a ferroelectric memory cell includes the steps of simultaneously opening top electrode and source/drain contacts to the ferroelectric memory cell, sputtering a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory cell, annealing the ferroelectric memory cell to simultaneously recover damage in a ferroelectric capacitor dielectric of the memory cell, and to silicidize the first metal layer in the source/drain contact, sputtering a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer, and selectively etching the first and second metal layers to form the local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell.

Abstract: Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.

Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber.