Patents Examined by C. J. Arbes
  • Patent number: 7832090
    Abstract: Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 16, 2010
    Inventors: Jonathan Bornstein, David Hansen, Steven W. Longcor
  • Patent number: 7832088
    Abstract: A method for using a segmented grounding system, including a bit including a coupling portion at a first end, and a generally tapered second end, a shaft with a first end configured to couple to the coupling portion of the bit, and a second end comprising a receiving structure, and a tool configured to couple to the receiving structure of the second end of the shaft.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: November 16, 2010
    Assignee: E & S Grounding Solutions, Inc.
    Inventors: David R. Stockin, Michael Esparza
  • Patent number: 7832092
    Abstract: A printed wiring board includes a plurality of conductor plates that includes at least one conductor plate that is used as a lead for electrical connection with an external circuit, the conductor plates being separated spatially from one another; an insulating layer formed on or across the conductor plates or both on and across the conductor plates; and a plurality of wiring patterns formed on the insulating layer. At least one of the conductor plates is electrically connected with at least one of the wiring patterns through a via-hole.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: November 16, 2010
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takehiro Shirai, Masayuki Iwase
  • Patent number: 7832089
    Abstract: Insulated electrically conductive fibers or microwires of sizes on the order of 1 mil (25 microns) diameter, so as to be suitable for processing into yarns or multi-microwire bundles, for example, for incorporation into conformable fabric products or for use as wearable electronic circuitry are made by coprocessing a core of a lower-melting-point metal within a sheath of a higher-melting-point polymer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: November 16, 2010
    Assignee: Pascale Industries, Inc.
    Inventors: Willorage Rathna Perera, Gerald J. Mauretti
  • Patent number: 7827681
    Abstract: There are provided the steps of mounting a semiconductor chip on a first substrate, providing an underfill resin between the semiconductor chip and the first substrate, forming a through hole on a second substrate, providing an electrode on the second substrate, bonding the first and second substrates to include the semiconductor chip through the electrode, and filling a sealing resin between the first and second substrates at a filling pressure capable of correcting a warpage generated on the semiconductor chip and the first substrate while discharging air from the through hole.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: November 9, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Nobuyuki Kurashima, Tadashi Arai, Hajime Iizuka
  • Patent number: 7823275
    Abstract: A method for making an electronic switch mountable on a circuit board includes the steps of: (A) providing a housing that includes a base having opposite inner and outer sides, and a cover body having a main portion that cooperates with the inner side of the base to define a chamber, and an end portion that cooperates with the outer side of the base to define a sealing space; (B) providing a terminal having a connecting part extending through the base and the sealing space for connection with the circuit board; (C) providing the base with a hollow portion that projects outwardly from the outer side thereof into the sealing space and that confines an air-discharge hole communicating fluidly with the chamber; (D) providing a first adhesive layer to seal the sealing space without covering the air-discharge hole; and (E) sealing the air-discharge hole.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 2, 2010
    Inventor: Tien-Ming Chou
  • Patent number: 7823283
    Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 7823281
    Abstract: An apparatus and method for crosstalk compensation in a jack of a modular communications connector includes a flexible printed circuit board connected to jack contacts and to connections to a network cable. The flexible printed circuit board includes conductive traces arranged as one or more couplings to provide crosstalk compensation.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: November 2, 2010
    Assignee: Panduit Corp.
    Inventors: Jack E. Caveney, Masud Bolouri-Saransar, Scott M. Lesniak
  • Patent number: 7823260
    Abstract: A method of manufacturing a metal-insulator-metal (MIM) capacitor that includes at least one of the following steps: Sequentially forming a bottom metal film, an insulating film, and a top metal film over a wafer. Forming a first pattern for etching the top metal film and the insulating film. Etching the top metal film and the insulating film, using the formed first pattern, and then stripping the first pattern. Conducting a heat treatment and a cooling split for the wafer. Forming a metal pattern for etching the bottom metal film. Etching the bottom metal film, using the formed metal pattern, and then stripping the metal pattern.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 2, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Baek-Won Kim
  • Patent number: 7818877
    Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 ?m or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: October 26, 2010
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Katsuyuki Masuda, Kiyoshi Hasegawa
  • Patent number: 7818876
    Abstract: A method is disclosed for the fabrication of feedthrough devices that can transmit a single or plurality of electrical signal(s) to or from within a leak-tight (hermetic) chamber from or to the outside of said leak-tight (hermetic) chamber. The invention allows materials known to be well-tolerated within the human body such as alumina-oxide ceramic and platinum to be used as raw materials in the fabrication of body-compatible, single or multi-channel leak-tight (hermetic) feedthroughs.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: October 26, 2010
    Inventor: Gregg Jorgen Suaning
  • Patent number: 7810232
    Abstract: A printed circuit board and manufacturing method thereof. A printed circuit board has an insulation substrate, which includes an insulation layer, a circuit pattern formed on one side of the insulation layer, and an interlayer passage joined to the insulation layer and configured to electrically connect with the circuit pattern, and a heat-release layer, which is stacked on the other side of the insulation layer to be stacked on the insulation substrate, can provide a high heat-releasing effect and high bending strength, by means of inner layers or ground layers formed by the heat-release layers.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 12, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Keun-Ho Kim, Dek-Gin Yang, Jong-Guk Kim, II-Kyoon Jeon, Eung-Suek Lee
  • Patent number: 7805834
    Abstract: The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided LCP, where both the high and low temperature LCP are provided with a z-axis connection. The single sided conductive layer is a bus layer to form z-axis conductive stud within the high and low temperature LCP. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: October 5, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: George E. White, Madhavan Swaminathan, Venkatesh Sundaram, Sidharth Dalmia
  • Patent number: 7802359
    Abstract: A method is described for manufacturing electronic assemblies (52). Electronic die (36) held in a plastic matrix (43) form a partially completed panel (35) of electronic assemblies (52). The panel (35) is adhesively mounted to a ceramic carrier (20) having multiple holes (22) there through. Conductive interconnects (38-1, 38-2, etc.) and other layers are applied to the panel, coupled to electrical contacts on the die (36) and external electrical contacts (39-1) for the panel (50). The panel (50) and the carrier (20) are separated and the panel singulated to release the finished electronic assemblies (52). Silicone is a preferred adhesive (27) and is dissolved using a non-polar solvent (70) that penetrates through the holes (22) in the carrier (20) to the adhesive (27). The adhesive (27) is preferentially applied using a transfer adhesive sandwich (24), that is, an adhesive layer (27) with removable plastic sheets (25, 26) on either side that can be peeled away from the adhesive (27).
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William H. Lytle, Craig S. Amrine
  • Patent number: 7797826
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: September 21, 2010
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
  • Patent number: 7797827
    Abstract: A method for installing compression connectors of various sizes and types on the end of a coaxial cable utilizes a tool having a base mounting a pair of movable anvils for engaging two different lengths of connectors. The movable anvils define an aperture which is shaped to permit easy entry and exit of a cable while still applying a suitable retention force to an inserted cable. A slidably mounted plunger cooperates with the anvils to compress a connector. One of the anvils has an aperture size that permits the anvil to squeeze or pinch an inserted cable and thereby restrain a cable longitudinally during initial seating of the connector onto a cable by means of the plunger.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: September 21, 2010
    Assignee: IDEAL Industries, Inc.
    Inventor: Robert W. Sutter
  • Patent number: 7793414
    Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: September 14, 2010
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Masud Beroz, David B. Tuckerman, Giles Humpston, Richard Dewitt Crisp
  • Patent number: 7793413
    Abstract: An electronic component mounting method for mounting a electronic component on a board, in which an Au bump provided at an electronic component is joined to a joining terminal formed on a board by using solder made of Sn or solder containing Sn and the electronic component is adhered to the board by means of thermosetting resin thereby to mount the electronic component on the board. The applied thermosetting resin is flown toward the outside by the lower surface of the electronic component, then a part of the solder particles contained within the thermosetting resin are made in contact with the side surfaces of the Au bumps which are heated to the temperature higher than the melting point of the solder and also another part of the solder particles are molten in a state of being sandwiched between the Au bumps and the electrodes. Thus, the diffusion of Sn into the Au bumps from the outside is promoted and so the density of Sn within the Au bumps can be increased.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Tadahiko Sakai, Hideki Eifuku
  • Patent number: 7793411
    Abstract: A method for manufacturing an electronic substrate including an electronic component bonded with adhesive to a base part, comprises (a) applying a droplet containing the adhesive to an area on the base part, the area facing to the electronic component, within a range substantially equal to a size of the electronic component by using a droplet ejection head moving in relatively to the base part, and (b) mounting the electronic component on the adhesive applied to the base part.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: September 14, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Tsuyoshi Shintate
  • Patent number: 7793409
    Abstract: A method forming at least a portion of a cable comprises providing at least one cable conductor core, extruding at least an inner layer of a polymeric insulation material over the at least one conductor core, providing a plurality of strength members having a coating of the polymeric insulation material, heating the at least one cable conductor core and the strength members, embedding the strength members into the inner layer of the cable conductor core, and extruding an outer layer of the polymeric insulation material over the cable conductor core and the plurality of strength members and bonding the outer layer to the inner layer and the coating to form the cable and provide a contiguous bond between the inner layer, the strength members, and the outer layer, wherein the polymeric insulation material of the inner layer, the strength member coating, and the outer layer are amended to enable the inner layer and the outer layer to melt at a greater rate than the strength member coating.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: September 14, 2010
    Assignee: Schlumberger Technology Corporation
    Inventor: Joseph Varkey