Patents Examined by Caleb E Henry
  • Patent number: 10436027
    Abstract: A method of evaluating a geometric parameter of a first fracture emanating from a first wellbore penetrating a subterranean formation is provided. The method includes the steps of forming the first fracture in fluid communication with the first wellbore; forming a second fracture in fluid communication with a second wellbore; measuring a first pressure change in the second wellbore in proximity to the first wellbore; and determining the geometric parameter of the first fracture using at least the measured first pressure change in an analysis which couples a solid mechanics equation and a pressure diffusion equation.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: October 8, 2019
    Assignee: STATOIL GULF SERVICES LLC
    Inventors: Günther Kampfer, Matthew A. Dawson
  • Patent number: 10436617
    Abstract: At least one aspect of the disclosure includes a method for start-up of a sensor comprising the steps of performing a factory adjustment during the manufacture of the sensor to generate factory adjustment data; permanently storing of the factory adjustment data from the factory adjustment in a memory of the sensor; prior to first use of the sensor, performing an initial user adjustment to generate initial user adjustment data; and permanently storing of the initial user adjustment data from the initial user adjustment in the memory. Another aspect of the disclosure improves the status evaluation of the sensor by enable permanent access to both the factory adjustment data and the initial user adjustment.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 8, 2019
    Assignee: Endress+Hauser Conducta GmbH+Co. KG
    Inventors: Bo Ottersten, Martin Freudenberger, Martin Lohmann
  • Patent number: 10431641
    Abstract: A thin film transistor (TFT) substrate includes a substrate and a first electrode disposed on the substrate. The first electrode is one of a source electrode and a drain electrode. The TFT further includes a first insulating layer disposed on the first electrode and a second electrode disposed on the first insulating layer. The second electrode is the other one of the source electrode and the drain electrode. The TFT additionally includes a semiconductor layer disposed on the first electrode, the first insulating layer, and the second electrode. The TFT further includes a second insulating layer disposed on the semiconductor layer. The TFT additionally includes a gate electrode disposed on the second insulating layer and overlapping the semiconductor layer. The TFT further includes a pixel electrode that includes a same material as the gate electrode and is electrically connected to the second electrode.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyunbeen Hwang, Minchul Shin
  • Patent number: 10432844
    Abstract: The present disclosure relates to an image pickup device that inhibits color mixture or noise, and an electronic apparatus. The image pickup device of the present disclosure includes an image plane phase difference detection pixel for image plane phase difference AF. The image plane phase difference detection pixel includes: a first photoelectric conversion section; an upper electrode section that is one of electrodes disposed facing each other, the upper electrode section being formed on a light incident side first photoelectric conversion section; and a lower electrode section that is another of the electrodes disposed facing each other, the lower electrode section being formed on an opposite side of the first photoelectric conversion section, the lower electrode section being multiple-divided at a position that avoids a center of the incident light. The present disclosure is applicable to image sensors.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 1, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kyohei Yoshimura, Toshifumi Wakano, Yusuke Otake
  • Patent number: 10418303
    Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10418391
    Abstract: Disclosed are a display substrate, a manufacture method thereof, and a display device. The display substrate comprises: a base substrate, and a metal layer, at least one insulating layer and a metal oxide conducting layer respectively on the base substrate, wherein, the at least one insulating layer is disposed between the metal layer and the metal oxide conducting layer; the metal oxide conducting layer is electrically connected to the metal layer through at least one via hole penetrating the at least one insulating layer; and the metal oxide conducting layer in the at least one via hole comprises metal particles produced by reducing the metal oxide conducting layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kui Gong, Qingli Feng
  • Patent number: 10418424
    Abstract: Disclosed are an organic light emitting display having touch sensors, which may achieve process simplification and cost reduction, and a method of fabricating the same. The organic light emitting display includes a plurality of touch electrodes disposed on an encapsulation unit disposed so as to cover light emitting elements, the touch electrodes are formed through a low-temperature deposition process and may thus have amorphous characteristics so as to prevent damage to an organic light emitting layer during formation of the touch electrodes, and the touch electrodes are disposed on the encapsulation unit without a separate attachment process and may thus simplify the overall process and reduce manufacturing costs.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 17, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Young Oh, Min-Joo Kim, Jae-Won Lee, Eun-Hye Lee
  • Patent number: 10411177
    Abstract: A light-emitting device, comprising: a substrate; a semiconductor stacking layer comprising a first type semiconductor layer on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises a bonding layer, a conductive layer, and a first barrier layer between the bonding layer and the conductive layer; wherein the conductive layer has higher standard oxidation potential than that of the bonding layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 10, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: De-Shan Kuo, Ting-Chia Ko, Chun-Hsiang Tu, Po-Shun Chiu
  • Patent number: 10411133
    Abstract: A manufacturing method of a polysilicon layer of a thin film transistor of a display device, includes: irradiating a first excimer laser beam having a first energy density to an amorphous silicon layer including an oxidation layer thereon, to form a first polysilicon layer including thereon portions of the oxidation layer at grain boundaries of the first polysilicon layer; removing the portions of the oxidation layer at the grain boundaries of the first polysilicon layer; and irradiating a second excimer laser beam having a second energy density of 80% to 100% of the first energy density to the first polysilicon layer from which the portions of the oxidation layer at the grain boundaries thereof are removed, to form a second polysilicon layer as the polysilicon layer of the thin film transistor.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Oh Seo, Byung Soo So, Dong-Min Lee, Dong-Sung Lee
  • Patent number: 10396180
    Abstract: A method and apparatus, the method comprising: forming at least two electrodes (23) on a release layer wherein the at least two electrodes are configured to enable a layer of two dimensional material (25) to be provided between the at least two electrodes; providing moldable polymer (27) overlaying the at least two electrodes; wherein the at least two electrodes and the moldable polymer form at least part of a planar surface (29).
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 27, 2019
    Assignee: EMBERION OY
    Inventors: Adam Robinson, Darryl Cotton, Alexander Bessonov, Richard White, Yinglin Liu
  • Patent number: 10395920
    Abstract: A method and composition for producing a low k dielectric film via chemical vapor deposition is provided. In one aspect, the method comprises the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising a silacyclic compound, and a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 2.7 or less.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 27, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Raymond Nicholas Vrtis, Robert Gordon Ridgeway, Jianheng Li, William Robert Entley, Jennifer Lynn Anne Achtyl, Xinjian Lei
  • Patent number: 10388581
    Abstract: A semiconductor device includes an insulating substrate, a semiconductor element provided on the insulating substrate, a case frame, a press-fit terminal, and a sealing member provided on an inner side of an inner wall part on the insulating substrate to seal the semiconductor element. The case frame is made of an insulating material and includes an outer wall part, an inner wall part, a recess bottom surface forming a recess together with the outer wall part and the inner wall part. The press-fit terminal includes a base part, a body part, and a press-in portion. The base part is embedded in the recess bottom surface and the body part stands upright from the recess bottom surface such that the body part extends between the inner wall part and the outer wall part, and the press-in portion protrudes up out of the recess.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Shinsuke Asada, Yoshitaka Kimura, Minoru Egusa
  • Patent number: 10388827
    Abstract: A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 20, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Hiroki Okamoto, Hiroaki Tamemoto, Junya Narita
  • Patent number: 10381533
    Abstract: Disclosed is an optical semiconductor device having an optical semiconductor mounting element including a recess. On an inner side face of the recess is a thermosetting resin composition for light reflection, which, after curing, can realize high reflectance in a range of visible light to near ultraviolet light, has excellent heat deterioration resistance and tablet moldability, and is less likely to cause burrs during transfer molding, and a process for producing the resin composition, and an optical semiconductor element mounting substrate and an optical semiconductor device using the resin composition. The heat curable resin composition for light reflection comprises a heat curable component and a white pigment and is characterized in that the length of burrs caused upon transfer molding under conditions of molding temperature of 100° C. to 200° C.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: August 13, 2019
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Hayato Kotani, Naoyuki Urasaki, Kanako Yuasa, Akira Nagai, Mitsuyoshi Hamada
  • Patent number: 10381280
    Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 13, 2019
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Nathapong Suthiwongsunthorn, John Ducyao Beleran, Serafin Padilla Pedron, Jr.
  • Patent number: 10374118
    Abstract: Semiconductor devices, such as photonics devices, employ substantially curved-shaped Silicon-Germanium (SiGe) structures and are fabricated using zero-change CMOS fabrication process technologies. In one example, a closed-loop resonator waveguide-coupled photodetector includes a silicon resonator structure formed in a silicon substrate, interdigitated n-doped well-implant regions and p-doped well-implant regions forming multiple silicon p-n junctions around the silicon resonator structure, and a closed-loop SiGe photocarrier generation region formed in a pocket within the interdigitated n-doped and p-doped well implant regions. The closed-loop SiGe region is located so as to substantially overlap with an optical mode of radiation when present in the silicon resonator structure, and traverses the multiple silicon p-n junctions around the silicon resonator structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 6, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Luca Alloatti, Rajeev Jagga Ram, Dinis Cheian
  • Patent number: 10367039
    Abstract: A display device including emitting areas is provided. The emitting areas of the display device may realize a different color each other. The display device includes light-emitting structures on the emitting areas. The adjacent light-emitting structures have different heights with respect to the lower substrate, such that a size of a non-emitting area between the adjacent emitting areas is reduced.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 30, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sung-Bin Shim, Ho-Won Choi, Eui-Doo Do, Moon-Bae Gee
  • Patent number: 10367170
    Abstract: A first electrode having light transmissivity is formed on a first surface of a first light transmissive substrate and. An organic functional layer includes a light-emitting layer and is located on an opposite side to the first light transmissive substrate with the first electrode interposed therebetween. A second electrode is located on an opposite side to the first electrode with the organic functional layer interposed therebetween. A second surface which is a surface of the first light transmissive substrate on an opposite side to the above-mentioned first surface is fixed to the second light transmissive substrate, which has a bending rigidity higher than that of the first light transmissive substrate. First irregularities are present in the second surface of the first light transmissive substrate, and second irregularities are positioned in a surface of the second light transmissive substrate which faces the first light transmissive substrate.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 30, 2019
    Assignee: PIONEER CORPORATION
    Inventor: Yasunobu Higashika
  • Patent number: 10361156
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheung-Hsuan Wei, Li-Yu Lee, Tai-Yang Wu
  • Patent number: 10355069
    Abstract: An organic light emitting diode display includes a substrate; a buffer layer on the substrate; a scan line running to a horizontal direction on the buffer layer; an intermediate insulating layer covering the scan line; a first trench having a segment shape apart from the scan line with a predetermined distance and exposing some of the substrate by patterning the intermediate insulating layer and the buffer layer; a data line running to a vertical direction on the substrate exposed by the first trench and on the intermediate insulating layer; a passivation layer covering the data line and the scan line; and a color filter filling into the trench and depositing on the passivation layer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Dosung Kim, Ryosuke Tani