Abstract: A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

Abstract: In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.

Abstract: There is provided a technique that includes: forming a film containing Si, O and N or a film containing Si and O on a substrate by performing a cycle a predetermined number of times under a condition where SiCl4 is not gas-phase decomposed, the cycle including non-simultaneously performing: (a) forming NH termination on a surface of the substrate by supplying a first reactant containing N and H to the substrate; (b) forming a SiN layer having SiCl termination formed on its surface by supplying the SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4; and (c) reacting the SiN layer having the SiCl termination with a second reactant containing O by supplying the second reactant to the substrate.

Abstract: Provided are a display substrate, a method for manufacturing the display substrate, and a display device. The display substrate has a display area, an opening area being provided in the display area, and the display substrate includes: a base substrate; at least one isolation structure provided on the base substrate and surrounding the opening area, and the isolation structure includes a first sidewall; a first filling structure provided on a side of the first sidewall away from the opening area, the first filling structure includes a second sidewall facing the first sidewall and a third sidewall facing away from the first sidewall; a first inorganic thin film disposed between the isolation structure and the filling structure; and a second inorganic thin film covering the isolation structure and the first filling structure.

Abstract: A semiconductor light emitting device includes a plane substrate having a flat substrate surface, a semiconductor light emitting element mounted on the substrate surface, and a lens formed of a resin which embeds the semiconductor light emitting element and condenses light emitted from the semiconductor light emitting element. A circular ring-shaped metal ring body surrounding the semiconductor light emitting element, and a plurality of regulation holes arranged inside the metal ring body at positions rotationally symmetric with respect to the center of the metal ring body are provided on the substrate surface. A bottom of the lens is defined by the metal ring body and the regulation holes. A body part of the lens has a plurality of valley portions extending toward the top of the lens from the positions of the regulation holes. The top of the lens has a surface as a spheroid surface with an axis vertical to the substrate surface and passing through the center of the metal ring body as a major axis.

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a display device and an anti-reflective layer disposed on the display device. The display device includes a plurality of sub-pixel areas distributed in an array manner. The anti-reflected layer includes a plurality of organic light-transmissive thin films corresponding to the sub-pixel areas. A plurality of inorganic nanoparticles are doped in the organic light-transmissive thin films. The inorganic nanoparticles at a side of the organic light-transmissive thin films away from the display device protrude from a surface of the organic light-transmissive thin films to form a plurality of nano moth-eye structures.

Abstract: A display substrate has blocking structures. The display substrate includes a base substrate, a display structure on a display area of the base substrate, at least one blocking structure on a peripheral area around the display area of the base substrate, and a first water-blocking layer on the substrate. The first water-blocking layer may cover the display structure and the at least one blocking structure. The blocking structure may be configured to block cracks generated on the first water-blocking layer at a side of the blocking structure opposite from the display area from propagating to the display area.

Abstract: A light-emitting device includes a light-emitting layer that includes, in each of a plurality of pixels: a light-emitting region in which a drive current flows between a first electrode and a second electrode; and a non-light-emitting region in which no drive current flows between the first electrode and the second electrode. The light-emitting region is divided into a plurality of subregions by a non-light-emitting region in a plan view.

Abstract: The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.

Abstract: A display device comprises: a display region having a plurality of pixels; and a frame region, the display region including: a thin-film transistor layer; a light-emitting-element layer provided above the thin-film transistor layer; and a sealing layer provided above the light-emitting-element layer, the light-emitting-element layer including: a first electrode; a second electrode; a light-emitting layer provided between the first electrode and the second electrode; and an electron-transport layer provided between the light-emitting layer and the second electrode, and the electron-transport layer containing: nanoparticles of metal oxide; and a binding resin.

Abstract: Disclosed are a SPAD pixel structure and a method of manufacturing the same, in which a cathode contact is formed on a back surface of a substrate instead of a front surface, thereby reducing or minimizing the distance between adjacent unit pixels and increasing the fill-factor of each unit pixel.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.

Abstract: A display unit includes a plurality of pixels, a reflector layer, and an auxiliary electrode. Each of the plurality of pixels has a first electrode, an organic layer, and a second electrode in this order. The organic layer and the second electrode are provided on the first electrode. The organic layer includes a light-emitting layer. The reflector layer has a light-reflecting surface around each of the pixels. The auxiliary electrode is provided on the reflector layer and is projected from an upper end of the light-reflecting surface. The auxiliary electrode has a portion which is exposed from the organic layer, and the exposed portion is covered with the second electrode.

Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.

Abstract: A method of manufacturing an optoelectronic device, including the steps of: a) arranging an active photosensitive diode stack on a first substrate; b) arranging an active light-emitting diode stack on a second substrate; c) after steps a) and b), transferring the active photosensitive diode stack onto the active light-emitting diode stack, and then removing the first substrate; and d) after step c), transferring the assembly comprising the active photosensitive diode stack and the active light-emitting diode stack onto an integrated control circuit previously formed inside and on top of a third substrate, and then removing the second substrate.

Abstract: A quantum dot composition includes a quantum dot, and a ligand bonded to a surface of the quantum dot, wherein the ligand includes a head portion bonded to the surface of the quantum dot and containing a polar solvent dissociative functional group, and a tail portion connected to the head portion. A quantum dot composition according to an embodiment is used to form an emission layer of a light emitting element to enhance luminous efficiency of the light emitting element including an emission layer formed through the quantum dot composition.

Abstract: A memory device includes a memory material portion, and an ovonic threshold switch selector element. The ovonic threshold switch selector element includes a first carbon-containing electrode comprising carbon and a metal, a second carbon-containing electrode comprising the carbon and the metal, and an ovonic threshold switch material portion located between the first electrode and the second electrode.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer on the first electrode in a diode region; a second semiconductor layer on the first electrode in an IGBT region; a semiconductor layer on the first and second semiconductor layers, a first upper layer of the semiconductor layer in the diode region including a first region adjacent to the IGBT region and a second region separated from the IGBT region, an impurity concentration being less in the first region than in the second region; a third semiconductor layer on the semiconductor layer; a fourth semiconductor layer of the third semiconductor layer in the IGBT region; a third electrode extending in a direction from the fourth semiconductor layer toward the semiconductor layer; and an insulating film between the second electrode and each of the third semiconductor layer, the semiconductor layer, and the third electrode.

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.