Patents Examined by Caleb E Henry
  • Patent number: 12660263
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is patterned to form a fin structure. The fin structure is recessed to form a recess in the fin structure. An epitaxial source/drain region is grown from the recess. A first silicide layer is formed on the epitaxial source/drain region. A first portion of the first silicide layer is thinned, while leaving a second portion of the first silicide layer un-thinned. A metal contact is formed in contact with the thinned first portion of the first silicide layer.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: June 16, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Yi-Hsien Chen, Chi Huang, Chih-Pin Tsao, Chun-Sheng Liang, Chih-Hao Chang
  • Patent number: 12660429
    Abstract: A display panel, a manufacturing method thereof, and a display device are provided. The display panel is divided into a bending area and a non-bending area, and includes a thin film transistor layer corresponding to the non-bending area, an organic filling layer corresponding to the bending area, and a pixel electrode. The pixel electrode in the bending area is connected to a source of the thin film transistor layer in the non-bending area through a metal trace, the organic filling layer includes a plurality of second via holes, and an organic photoresist is filled in the plurality of second via holes.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 16, 2026
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Junyan Hu
  • Patent number: 12660422
    Abstract: A display device includes: a substrate; an insulation layer that is positioned on the substrate and includes a plurality of openings; a plurality of emission layers that are positioned in the openings; and a plurality of spacers that are positioned on the insulation layer, wherein an area where the emission layers are positioned defines light emitting regions on a plane, at least one of the spacers has a shape of a circle, a regular polygon having five or more sides, or a regular polygon with at least one rounded corner and five or more sides, a planar area of at least one of the spacers is larger than a planar area of the smallest light emitting region, and the number of the spacers positioned in the predetermined region is at least 30% of the number of the light emitting regions arranged in the predetermined region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: June 16, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soo-Young Jung, Sung Jae Jung
  • Patent number: 12660480
    Abstract: Provided is a display device including a base layer, a pixel defining film, a display element layer including a light-emitting element divided by a pixel defining film, an encapsulation substrate on the display element layer, and a filling layer between the display element layer and the encapsulation substrate and including a filler derived from a mixture having a first polymer compound containing a first monomer represented by Formula 1 below, a second polymer compound containing a second monomer represented by Formula 2 below, and a plurality of crosslinking compounds.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: June 16, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yongchan Ju, Yeonguk Kim, Jongwoo Kim, Heeyeon Park, Changyeong Song, Hyein Yang, Soyoung Oh, Jongkwang Yun, Woosuk Jung, Jaeheung Ha
  • Patent number: 12660394
    Abstract: A display device includes a first electrode, an outer electrode surrounding the first electrode, a bank overlapping the outer electrode in a plan view, the bank including an opening that exposes the first electrode, a light emitting element disposed on the first electrode and in the opening of the bank, and a second electrode disposed on the light emitting element. The outer electrode may be electrically disconnected from the first electrode upon a bad contact between a light emitting member and the outer electrode. As a result, defective pixels can be repaired.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: June 16, 2026
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seul Ki Kim, Tae Jin Kong, Myeong Hee Kim, Ji Eun Park, Myeong Su So
  • Patent number: 12660434
    Abstract: Provided is a display panel, including: a base substrate, including a display area and a peripheral area surrounding the display area; a plurality of pixel units, disposed in the display area; a barrier structure, disposed in the peripheral area; at least one first power line, disposed in the peripheral area; and, a row drive circuit, disposed in the peripheral area, wherein orthographic projections of any two of the following structures on the base substrate are at least partially overlapped with each other: the barrier structure, the at least one first power line, and the row drive circuit.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: June 16, 2026
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Meng Li, Binyan Wang, Tianyi Cheng, Feng Wei, Cong Liu, Kaipeng Sun, Shiqian Dai
  • Patent number: 12652943
    Abstract: An apparatus for manufacturing a display device includes a chamber in which a display substrate is arranged, a lamp portion arranged outside or inside the chamber irradiating light, and a mask arranged inside the chamber to expose a portion of the display substrate and to shield another portion of the display substrate. The mast includes a hole through which the light irradiated from the lamp portion passes, and the lamp portion includes a flash lamp or a xenon lamp.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: June 9, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Changyun Moon, Gihyun Lee, Ilseob Yoon
  • Patent number: 12648296
    Abstract: Provided is an organic photodiode including a first electrode, a common electrode facing the first electrode, and a photoactive layer located between the first electrode and the common electrode, wherein the photoactive layer includes a donor layer and an acceptor layer, the donor layer includes a donor compound represented by Formula 110, the acceptor layer includes a first acceptor layer including a first acceptor compound and a second acceptor compound, each independently represented by Formula 120, and the first acceptor compound and the second acceptor compound are different from each other. Formulae 110 and 120 are each as described herein.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: June 2, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jinsoo Jung, Minsoo Choi, Seokgyu Yoon
  • Patent number: 12648138
    Abstract: A semiconductor storage device includes: a first stack having a first insulation film and a first conductive film alternately stacked in a first direction; a plurality of first column portions respectively including a first semiconductor portion extending in the first stack in the first direction and a charge trapping film provided on an outer circumferential surface of the first semiconductor portion; and a first isolation portion penetrating through an upper-layer portion of the first stack in the first direction, extending in a second direction that crosses the first direction, including a second insulation film and a third insulation film arranged via the second insulation film, and configured to electrically isolate the first conductive film included in the upper-layer portion of the first stack in a third direction that crosses the first and second directions.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: June 2, 2026
    Assignee: Kioxia Corporation
    Inventors: Shun Shimizu, Takashi Ishida
  • Patent number: 12635256
    Abstract: An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: May 19, 2026
    Assignee: STMicroelectronics France
    Inventor: Philippe Galy
  • Patent number: 12635567
    Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 19, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Bret K. Street, Kyle K. Kirby, Wei Zhou, Thiagarajan Raman
  • Patent number: 12628494
    Abstract: An electroluminescent device includes a first electrode; a second electrode spaced apart from the first electrode; and a light emitting layer disposed between the first electrode and the second electrode, the light emitting layer includes semiconductor nanoparticles, wherein the semiconductor nanoparticles do not include cadmium, the semiconductor nanoparticles have a core shell structure, the semiconductor nanoparticles include zinc, selenium, tellurium, and sulfur, wherein in a two dimensional image obtained by an electron microscopy analysis, the semiconductor nanoparticles show an average value of a circularity defined by the following equation of greater than or equal to about 0.8 and less than or equal to about 1: circularity = 4 ? ? × Area [ Perimeter ] 2 wherein Area is an area of a two dimensional image of an individual semiconductor nanoparticle, and Perimeter is a circumference of the two dimensional image of the individual semiconductor nanoparticle.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 12, 2026
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG DISPLAY CO., LTD.
    Inventors: Yuho Won, Sung Woo Kim, Eun Joo Jang, Hyo Sook Jang
  • Patent number: 12628411
    Abstract: A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. The channel structures have opposing ends that are uncovered. Sidewall constraints are formed at the opposing ends of the channel structures. Each pair of the sidewall constraints laterally bounds a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region. S/D structures are formed on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: May 12, 2026
    Assignee: Tokyo Electron Limited
    Inventor: Jeffrey Smith
  • Patent number: 12628705
    Abstract: An opto-electronic device includes: (i) a substrate having a surface; (ii) a first electrode disposed over the surface; (iii) a semiconducting layer disposed over at least a portion of the first electrode; (iv) a second electrode disposed over the semiconducting layer; (v) a nucleation inhibiting coating disposed over at least a portion of the second electrode; (vi) a patterning structure disposed over the surface, the patterning structure providing a shadowed region between the patterning structure and the second electrode; (vii) an auxiliary electrode disposed over the surface; and (viii) a conductive coating disposed in the shadowed region, the conductive coating electrically connecting the auxiliary electrode and the second electrode.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: May 12, 2026
    Assignee: OTI Lumionics Inc.
    Inventors: Zhibin Wang, Michael Helander
  • Patent number: 12628553
    Abstract: Disclosed in embodiments of the present invention are a quantum dot material, a light-emitting device and a manufacturing method therefor, and a display apparatus. The quantum dot material comprises: a quantum dot and at least one first ligand connected to the surface of the quantum dot. The first ligand comprises: an inner group connected to the quantum dot, a first photosensitive group connected to the inner group, and an outer group connected to the first photosensitive group, the inner group being configured to adsorb the quantum dot material on the surface of a carrier film layer, the first photosensitive group being configured to break under the irradiation of ultraviolet light, such that the outer group is separated from the inner group, and the outer group being configured to ionize in an aqueous solution to make the quantum dot material electropositive or electronegative.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: May 12, 2026
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Zhuo Li
  • Patent number: 12622180
    Abstract: Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 5, 2026
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Max E. Nielsen, Alexander Louis Braun, Daniel George Dosch, Kurt Pleim, Haitao O. Dai, Charles R. Wallace
  • Patent number: 12615947
    Abstract: According to one embodiment, a display device manufacturing method includes forming a lower electrode, forming an insulating layer overlapping the lower electrode, forming a first aluminum layer, forming a middle layer, forming a second aluminum layer, forming a thin film, forming a partition including a lower portion including the first aluminum layer, the middle layer and the second aluminum layer and an upper portion including the thin film and protruding from a side surface of the lower portion by etching the first aluminum layer, the middle layer, the second aluminum layer and the thin film, forming an organic layer on the lower electrode, and forming an upper electrode on the organic layer and is in contact with the lower portion of the partition.
    Type: Grant
    Filed: January 24, 2023
    Date of Patent: April 28, 2026
    Assignee: MAGNOLIA WHITE CORPORATION
    Inventors: Yuya Yamamoto, Nobuo Imai
  • Patent number: 12615913
    Abstract: A method for fabricating a display device that easily achieves higher resolution is provided. A display device having both high display quality and high resolution is provided. A first EL film is formed over a first pixel electrode and a second pixel electrode; a first sacrificial film is formed to cover the first EL film; the first sacrificial film and the first EL film are etched to expose the second pixel electrode and to form a first EL layer over the first pixel electrode and a first sacrificial layer over the first EL layer; and the first sacrificial layer is removed. The first EL film and the second EL film are etched by dry etching, and the first sacrificial layer is removed by wet etching.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: April 28, 2026
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daiki Nakamura, Tomoya Aoyama, Yasutaka Nakazawa, Rai Sato, Seiji Yasumoto, Kiyofumi Ogino, Takashi Shiraishi
  • Patent number: 12610569
    Abstract: A silicon carbide semiconductor device comprises a SiC substrate, a drift layer disposed on the substrate, a plurality of first doping regions formed near a surface of the drift layer, a plurality of second doping regions formed near the surface of the drift layer and between the first doping regions and a first metal layer disposed on the surface of the drift layer. The first metal layer forms an Ohmic contact with the second doped region. The drift layer has a first doping concentration of a first conductivity type and each of the second doping regions has a second doping concentration of the first conductivity type, which is higher than the first doping concentration. Each of the first doping regions has a first depth and each of the second doping regions has a second depth which is smaller than the first depth.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: April 21, 2026
    Assignee: Fast SiC Semiconductor Incorporated
    Inventors: Fu-Jen Hsu, Cheng-Tyng Yen, Hsiang-Ting Hung
  • Patent number: 12604596
    Abstract: The present invention relates to a method for manufacturing a perovskite solar cell and a perovskite solar cell manufactured thereby and, more specifically, to a method for manufacturing a perovskite solar cell and a perovskite solar cell manufactured thereby, wherein the method comprises the steps of: (S1) applying a) an oxidative agent, b) ultraviolet light and ozone, c) oxygen plasma, or d) nitrogen dioxide gas to a hole transport layer (HTL) of a laminate in which a substrate layer, a first electrode layer, and the hole transport layer (HTL) containing a metal oxide are sequentially laminated, to oxidize the metal oxide; and (S2) sequentially laminating a perovskite layer, an electron transport layer, and a second electrode layer on the hole transport layer of the laminate.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 14, 2026
    Assignee: HANWHA SOLUTIONS CORPORATION
    Inventor: An Na Cho