Abstract: Provided is an organic photodiode including a first electrode, a common electrode facing the first electrode, and a photoactive layer located between the first electrode and the common electrode, wherein the photoactive layer includes a donor layer and an acceptor layer, the donor layer includes a donor compound represented by Formula 110, the acceptor layer includes a first acceptor layer including a first acceptor compound and a second acceptor compound, each independently represented by Formula 120, and the first acceptor compound and the second acceptor compound are different from each other. Formulae 110 and 120 are each as described herein.

Abstract: An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

Abstract: An electroluminescent device includes a first electrode; a second electrode spaced apart from the first electrode; and a light emitting layer disposed between the first electrode and the second electrode, the light emitting layer includes semiconductor nanoparticles, wherein the semiconductor nanoparticles do not include cadmium, the semiconductor nanoparticles have a core shell structure, the semiconductor nanoparticles include zinc, selenium, tellurium, and sulfur, wherein in a two dimensional image obtained by an electron microscopy analysis, the semiconductor nanoparticles show an average value of a circularity defined by the following equation of greater than or equal to about 0.8 and less than or equal to about 1: circularity = 4 ? ? × Area [ Perimeter ] 2 wherein Area is an area of a two dimensional image of an individual semiconductor nanoparticle, and Perimeter is a circumference of the two dimensional image of the individual semiconductor nanoparticle.

Abstract: A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. The channel structures have opposing ends that are uncovered. Sidewall constraints are formed at the opposing ends of the channel structures. Each pair of the sidewall constraints laterally bounds a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region. S/D structures are formed on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.

Abstract: An opto-electronic device includes: (i) a substrate having a surface; (ii) a first electrode disposed over the surface; (iii) a semiconducting layer disposed over at least a portion of the first electrode; (iv) a second electrode disposed over the semiconducting layer; (v) a nucleation inhibiting coating disposed over at least a portion of the second electrode; (vi) a patterning structure disposed over the surface, the patterning structure providing a shadowed region between the patterning structure and the second electrode; (vii) an auxiliary electrode disposed over the surface; and (viii) a conductive coating disposed in the shadowed region, the conductive coating electrically connecting the auxiliary electrode and the second electrode.

Abstract: Disclosed in embodiments of the present invention are a quantum dot material, a light-emitting device and a manufacturing method therefor, and a display apparatus. The quantum dot material comprises: a quantum dot and at least one first ligand connected to the surface of the quantum dot. The first ligand comprises: an inner group connected to the quantum dot, a first photosensitive group connected to the inner group, and an outer group connected to the first photosensitive group, the inner group being configured to adsorb the quantum dot material on the surface of a carrier film layer, the first photosensitive group being configured to break under the irradiation of ultraviolet light, such that the outer group is separated from the inner group, and the outer group being configured to ionize in an aqueous solution to make the quantum dot material electropositive or electronegative.

Abstract: Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.

Abstract: According to one embodiment, a display device manufacturing method includes forming a lower electrode, forming an insulating layer overlapping the lower electrode, forming a first aluminum layer, forming a middle layer, forming a second aluminum layer, forming a thin film, forming a partition including a lower portion including the first aluminum layer, the middle layer and the second aluminum layer and an upper portion including the thin film and protruding from a side surface of the lower portion by etching the first aluminum layer, the middle layer, the second aluminum layer and the thin film, forming an organic layer on the lower electrode, and forming an upper electrode on the organic layer and is in contact with the lower portion of the partition.

Abstract: A method for fabricating a display device that easily achieves higher resolution is provided. A display device having both high display quality and high resolution is provided. A first EL film is formed over a first pixel electrode and a second pixel electrode; a first sacrificial film is formed to cover the first EL film; the first sacrificial film and the first EL film are etched to expose the second pixel electrode and to form a first EL layer over the first pixel electrode and a first sacrificial layer over the first EL layer; and the first sacrificial layer is removed. The first EL film and the second EL film are etched by dry etching, and the first sacrificial layer is removed by wet etching.

Abstract: A silicon carbide semiconductor device comprises a SiC substrate, a drift layer disposed on the substrate, a plurality of first doping regions formed near a surface of the drift layer, a plurality of second doping regions formed near the surface of the drift layer and between the first doping regions and a first metal layer disposed on the surface of the drift layer. The first metal layer forms an Ohmic contact with the second doped region. The drift layer has a first doping concentration of a first conductivity type and each of the second doping regions has a second doping concentration of the first conductivity type, which is higher than the first doping concentration. Each of the first doping regions has a first depth and each of the second doping regions has a second depth which is smaller than the first depth.

Abstract: The present invention relates to a method for manufacturing a perovskite solar cell and a perovskite solar cell manufactured thereby and, more specifically, to a method for manufacturing a perovskite solar cell and a perovskite solar cell manufactured thereby, wherein the method comprises the steps of: (S1) applying a) an oxidative agent, b) ultraviolet light and ozone, c) oxygen plasma, or d) nitrogen dioxide gas to a hole transport layer (HTL) of a laminate in which a substrate layer, a first electrode layer, and the hole transport layer (HTL) containing a metal oxide are sequentially laminated, to oxidize the metal oxide; and (S2) sequentially laminating a perovskite layer, an electron transport layer, and a second electrode layer on the hole transport layer of the laminate.

Abstract: To provide a light-emitting element in which an organic compound layer can be processed at once by a photolithography technique. A first electrode and an organic compound layer including an electron-injection layer are formed over an insulating surface. The electron-injection layer is the outermost layer of the organic compound layer and contains an organic compound having a basic skeleton and an acid dissociation constant pKa of greater than or equal to 1. A sacrificial layer and a mask are formed over the electron-injection layer and the sacrificial layer is processed into an island shape using the mask. With use of the island-shaped sacrificial layer as a mask, the organic compound layer is processed into an island shape to cover the first electrode. Part of the island-shaped sacrificial layer is removed with an acidic chemical solution to expose the electron-injection layer. A second electrode is formed to cover the electron-injection layer.

Abstract: A semiconductor device includes a first transistor cell. The first transistor cell generates a first current signal and a second current signal indicating a bit of a physical unclonable function. The first transistor cell includes a first transistor, a second transistor and a third transistor. The first transistor outputs the first current signal. The second transistor generates the first current signal from a first source/drain structure of the second transistor, and generates the second current signal from a second source/drain structure of the second transistor. The third transistor outputs the second current signal. The first transistor, the second transistor and the third transistor are stacked in order along a first direction. The first source/drain structure of the second transistor and the second source/drain structure of the second transistor are arranged along a second direction different from the first direction.

Abstract: A substrate processing method includes preparing a substrate having a target film including silicon, carbon, and nitrogen on a surface of the substrate; supplying hydrogen gas and oxygen gas to the target film to oxidize a surface layer of the target film and form an oxide film; and etching the oxide film.

Abstract: Provided are a compound represented by Formula 1, an organic electric element including a first electrode, a second electrode, and an organic material layer between the first electrode and the second electrode, and an electronic device thereof, wherein the compound represented by Formula 1 is included in the organic material layer, thereby the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time can be improved.

Abstract: A method of manufacturing a light-emitting device including a body portion and a light-emitting portion arranged in the body portion and configured to emit light to the outside. The light-emitting portion includes a plurality of pixels. At least two of the pixels are configured to emit pieces of light having different wavelengths from each other.

Abstract: Semiconductor devices may include a first stack structure including interlayer insulating layers and gate electrodes alternately stacked in a first direction perpendicular to an upper surface of a substrate on a first region of the substrate and including a first lower stack structure and a first upper stack structure, a second stack structure including the interlayer insulating layers and sacrificial insulating layers alternately stacked in the first direction on a second region of the substrate and including a second lower stack structure and a second upper stack structure, a channel structure penetrating the first upper stack structure and the first lower stack structure, extending in the first direction, and including a channel layer, and an align key structure penetrating the second lower stack structure and extending in the first direction. The second upper stack structure may include a first align key region on the align key structure.

Abstract: A display apparatus includes: a first substrate including a display area, and a pad area outside the display area; a lower conductive layer on the first substrate, and including a fan-out wiring extending from the pad area to the display area; a first inorganic insulating layer on the lower conductive layer; a semiconductor layer on the first inorganic insulating layer, and overlapping with the display area; a second inorganic insulating layer covering the semiconductor layer, and overlapping with the display area and the pad area; a pad electrode on the second inorganic insulating layer, the pad electrode overlapping with the pad area, and electrically connected to the fan-out wiring; and a display element layer on the second inorganic insulating layer, and including a display element overlapping with the display area.

Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally on a step of the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and an etch stop material formed around the wordline contact and on the polysilicon wordline, where the etch stop material extends to an outside corner of the step, the etch stop material is absent from a sidewall of the step, and the etch stop material is undercut at the outside corner of the step. Other embodiments are disclosed and claimed.