Abstract: An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.

Abstract: A light emitting element ink and a method of manufacturing a display device are provided. The light emitting element ink includes a light emitting element solvent, a light emitting element dispersed in the light emitting element solvent, the light emitting element including a plurality of semiconductor layers and an insulating film surrounding outer surfaces of the semiconductor layers, a thickener dispersed in the light emitting element solvent, wherein a compound of the thickener includes a functional group capable of forming a hydrogen bond together with a compound of the light emitting element solvent or another compound of the thickener and the compound of the thickener is represented by Chemical Formula 1.

Abstract: An apparatus for manufacturing a display device, includes: a stage; a temperature controlling portion on the stage, and to receive a member seated on the temperature controlling portion; and a jig portion facing the temperature controlling portion, the jig portion to move linearly, and to receive an adhesive member. The jig portion includes: a first support plate; a second support plate facing the first support plate; and a pressurization plate on the first support plate and the second support plate, the pressurization plate to receive the adhesive member thereon. An end of the pressurization plate is spaced further from the member than an end of the first support plate and an end of the second support plate when the member is seated on the temperature controlling portion.

Abstract: A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.

Abstract: Provided is a layout structure adapted for a signal format converter. The layout structure includes a first and a second capacitor array. The first capacitor array is disposed on one side of a reference axis, and includes multiple first capacitor units that form multiple first capacitors. The first capacitors respectively have multiple first capacitances. The second capacitor array is disposed on the other side of the reference axis, and includes multiple second capacitor units that form multiple second capacitors. The second capacitors respectively have multiple second capacitances. The first capacitors respectively correspond to the second capacitors. Each first capacitor and each corresponding second capacitor are symmetrical with respect to the reference axis, or each first capacitor and each corresponding second capacitor are separated from each other by the same distance. Each first capacitor and each corresponding second capacitor have the same capacitance.

Abstract: A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.

Abstract: The present disclosure provides a lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method includes: providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate; forming a drain region in the drift region, forming a source region in the body region, and forming, on the body region, a gate structure extending to the drift region; implanting ions of a first type, so as to form, at a bottom of the drift region, first ion implantation regions extending along a direction from the gate structure to the drain region; forming, above the first ion implantation regions, a plurality of mutually spaced deep trench structures and fin structures between adjacent ones of the deep trench structures; and implanting ions of a second type in the deep trench structures to form second ion implantation regions.

Abstract: A display device includes a plurality of pixel electrodes, a common electrode common to the plurality of pixel electrodes, and a light-emitting layer sandwiched between the plurality of pixel electrodes and the common electrode. The light-emitting layer includes quantum dots covered by ferritin. Each of the plurality of pixel electrodes and the quantum dots are bonded via a peptide modifying the ferritin.

Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.

Abstract: The present disclosure relates to a chip-on-film bonding structure, a display module, and a terminal equipment. The chip-on-film bonding structure includes: a chip on film including a first pin, the first pin including a first end and a second end that are arranged to be opposite to each other; and a flexible circuit board including a second pin connected to the first pin, the second pin including a third end and a fourth end that are arranged to be opposite to each other; in which the first end and the third end overlap to form a first active contact region; and the second end and the fourth end respectively extend outward from two opposite sides of the first active contact region, to form a first exposed region at the second end and to form a second exposed region at the fourth end.

Abstract: A display device may include a substrate including a display area and a bending area, a buffer layer disposed on the substrate, a first dummy pattern disposed in the bending area on the buffer layer; a first insulating layer disposed on the buffer layer, the first insulating layer exposing an upper surface of the first dummy pattern, a second insulating layer disposed on the first insulating layer, the second insulating layer having an opening exposing an upper surface of the first dummy pattern, a second dummy pattern disposed on the first dummy pattern, and a transmission line disposed on the second dummy pattern.

Abstract: A substrate assembly and a display device are provided. The substrate assembly includes a substrate, a first conductive line, and a second conductive line. The first conductive line is disposed on the substrate, wherein a voltage is applied to the first conductive line. The second conductive line is disposed on the substrate, wherein in a top view, at least a portion of the second conductive line extends along a first direction. The first conductive line and the second conductive line are at least partially overlapped in a normal direction of the substrate. A distance between the first conductive line and the second conductive line in the normal direction is greater than or equal to 3500 angstroms, and less than or equal to 4500 angstroms.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

Abstract: A tiled electronic device includes a plurality of display panels, and at least one of the display panels includes a flexible substrate, a pixel, and two signal wires. The flexible substrate has a display portion and a bent portion connected to the display portion. The pixel is disposed on the display portion. The signal wires are disposed on the flexible substrate, and electrically connected to the pixel. Each of the signal wires has a first segment disposed on the display portion, and a second segment disposed on the bent portion. The two first sections have a first pitch, and the two second sections have a second pitch. The first pitch is different than the second pitch.

Abstract: An organic light-emitting diode includes: a first electrode and a second electrode facing each other; an organic emission layer between the first electrode and the second electrode; and a hole injection layer between the first electrode and the organic emission layer, wherein the hole injection layer includes a second metal compound layer and a second metal layer, the second metal compound layer being between the first electrode and the organic emission layer, and the second metal layer being between the second metal compound layer and the organic emission layer.

Abstract: The invention relates to a lead frame assembly comprising a plurality of regularly arranged lead frames, each of which is suitable for electrically contacting components, comprises at least two lead frame elements distanced laterally by a recess and which are provided as electrical connections of different polarity, and has at least one anchoring element, which is suitable for anchoring a housing body of the component, the lead frame elements being thinned, flat regions of the lead frame, and the at least one anchoring element protrudes from a plane of the lead frame elements in the form of a pillar, and a plurality of connection elements, which in each case connects two lead frame elements of adjacent lead frames to one another, the two connected lead frame elements being provided as terminals of different polarity.

Abstract: An organic light emitting diode having a substrate, a first electrode, a hole transporting layer proximate the first electrode, a second electrode, an electron transporting layer proximate the second electrode, and an emissive layer between the hole transporting layer and the electron transporting layer. The emissive layer includes a square planar tetradentate platinum or palladium complex, and excimers formed by two or more of the complexes are aligned such that emitting dipoles of the excimers are substantially parallel to a surface of the substrate.

Abstract: A package mold according to some embodiments includes a first mold body and a second mold body, a mold cavity in the first mold body, a gate in a first side of the mold cavity for supplying liquid mold compound into the mold cavity, a longitudinal vent for releasing gas from the mold cavity in a second side of the mold cavity opposite the first side of the mold cavity, and a transverse vent for releasing gas from the mold cavity in a third side of the mold cavity that extends between the first and second sides of the mold cavity. Methods of packaging an electronic device using the package mold and resulting packaged devices are also disclosed.

Abstract: Provided is a light-emitting element to highly efficiently emit light in different colors. The light-emitting element includes: a cathode; an anode; a light-emitting layer formed between the cathode and the anode, and including a plurality of light-emitting regions respectively emitting light of different wavelengths; and an electron-transport layer formed between the cathode and the light-emitting layer, and including a plurality of regions each corresponding to one of the light-emitting regions. The electron-transport layer includes a Zn1-XMgXO film (where X is 0?X<1). Of the plurality of regions included in the electron-transport layer, a region, corresponding to one of the light-emitting regions that emits light of a shorter wavelength, is higher in composition ratio X of Mg and/or less in thickness of the Zn1-XMgXO film.

Abstract: In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.