Patents Examined by Caleb Henry
  • Patent number: 10283450
    Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Patent number: 10249832
    Abstract: To provide an organic electroluminescence device having a high luminous efficiency and a novel compound that can be used as a material for an organic electroluminescence device having a high luminous efficiency. A compound represented by the following formula (3-I), wherein at least one of R1 to R7 and R10 to R11 is —N(R36)(R37). R31 to R37 are independently a hydrogen atom, a substituted or unsubstituted alkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted cycloalkyl group including 3 to 50 ring carbon atoms, a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: April 2, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Ryota Takahashi, Hidetsugu Ikeda, Keita Seda, Yuki Nakano
  • Patent number: 10243016
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 10243069
    Abstract: The present description relates to a gallium nitride transistor which includes at least one source/drain structure having low contact resistance between a 2D electron gas of the gallium nitride transistor and the source/drain structure. The low contact resistance may be a result of at least a portion of the source/drain structure being a single-crystal structure abutting the 2D electron gas. In one embodiment, the single-crystal structure is grown with a portion of a charge inducing layer of the gallium nitride transistor acting as a nucleation site.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Seung Hoon Sung, Sanaz Gardner, Robert S. Chau
  • Patent number: 10236317
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 10217948
    Abstract: To provide an organic electroluminescence device having a high luminous efficiency and a novel compound that can be used as a material for an organic electroluminescence device having a high luminous efficiency. A compound represented by the following formula (3-I), wherein at least one of R1 to R7 and R10 to R11 is —N(R36)(R37). R31 to R37 are independently a hydrogen atom, a substituted or unsubstituted alkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted cycloalkyl group including 3 to 50 ring carbon atoms, a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: February 26, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Ryota Takahashi, Hidetsugu Ikeda, Keita Seda, Yuki Nakano
  • Patent number: 10211081
    Abstract: A processing method for processing a workpiece includes a holding step of holding the front surface side of the workpiece on which an alignment mark is formed by a holding table having a holding surface that reflects a near-infrared ray and exposing the back surface side and an imaging step of emitting the near-infrared ray toward the back surface side of the workpiece held by the holding table and imaging the workpiece by an imaging unit that has sensitivity to the near-infrared ray and faces the back surface side of the workpiece to form a captured image. The processing method also includes an alignment mark detection step of detecting the alignment mark based on the captured image and a processing step of processing the workpiece held by the holding table by a processing unit based on the detected alignment mark.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 19, 2019
    Assignee: Disco Corporation
    Inventor: Satoshi Hanajima
  • Patent number: 10209619
    Abstract: A semiconductor device production composition comprises a product obtained by mixing a metal compound and a compound represented by Formula (1) in a first organic solvent, and a second organic solvent. R and R? each independently represent a hydrogen atom, a linear or cyclic alkyl group having a carbon number of 2 to 20, a linear or cyclic alkylcarbonyl group having a carbon number of 2 to 20, an aryl group having a carbon number of 6 to 20, or an aryloxy group having a carbon number of 6 to 20, and part of the hydrogen atoms in the cyclic alkyl, cyclic alkylcarbonyl, aryl, or aryloxy group are substituted or unsubstituted.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: February 19, 2019
    Assignee: JSR CORPORATION
    Inventors: Hisashi Nakagawa, Ryuichi Saitou, Shunsuke Kurita, Tatsuya Sakai
  • Patent number: 10211122
    Abstract: An object of the present invention is to provide a semiconductor module with high heat dissipation at a low cost. A semiconductor module according to the present invention includes: a case having a hollow portion; a base board made of an aluminum alloy having a first portion corresponding to the hollow portion of the case, and a second portion corresponding to a main body portion of the case, the base board being attached to a bottom face of the case via the second portion; a ceramic insulating substrate disposed on the first portion of the base board; a wiring pattern disposed on the ceramic insulating substrate; semiconductor elements disposed on the wiring pattern; metal wiring boards connected to the semiconductor elements; and a sealing resin that seals the hollow portion of the case.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hajime Kato, Mikio Ishihara, Yuji Imoto
  • Patent number: 10205114
    Abstract: A composition suitable for use in an organic light-emitting layer (103) of an organic light-emitting device having an anode (101) and a cathode (105), the composition comprising a fluorescent light-emitting material, a first triplet-accepting material and a second triplet-accepting material that is different from the first triplet-accepting material. The fluorescent light-emitting material may be a repeat unit of a light-emitting polymer, and the first and second triplet-accepting materials may independently be repeat units of the light-emitting polymer or may be mixed with the fluorescent light-emitting material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 12, 2019
    Assignees: Cambridge Display Technology Limited, Sumitomo Chemical Company Limited
    Inventors: Martina Pintani, Ian Johnson, Francesco Di Stasio, Martin Humphries, Jonathan Pillow, Ruth Pegington, James Morey
  • Patent number: 10197417
    Abstract: Textiles coupled with electrical components that are responsive to actions of the wearer and the surrounding environment. The textiles comprise a variety of sensors that interface with the cloud, networks, and devices. The textiles monitor physiological characteristics of the wearer. Objects in the environment may interact with the electrical components of the textiles. Micro-Electro-Mechanical Systems that include electrical components, such as, accelerometers, gyroscopes, Bluetooth chips, NFC chips, and RF tags integrate with the textiles to wirelessly communicate with networks.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 5, 2019
    Inventors: James D Logan, Eric Carr
  • Patent number: 10192955
    Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Moriz Jelinek, Hans-Joachim Schulze, Werner Schustereder, Michael Stadtmueller
  • Patent number: 10187060
    Abstract: The invention relates to a lighting device comprising an illuminant embodied as an OLED, and comprising a capacitive switching means, which are arranged on a substrate, wherein the illuminant has a first electrically conductive electrode and a second electrically conductive electrode, wherein a layer comprising organic, electroluminescent material is arranged between the first electrode and the second electrode, wherein the switching means has an electrode, wherein one electrode from the first electrode or the second electrode of the illuminant together with the electrode of the switching means is arranged in one plane, wherein a nonconductive spacing amounting to between 100 ?m and 700 ?m, more particularly between 400 ?m and 600 ?m, is present between said one electrode of the illuminant and the electrode of the switching means in the plane.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 22, 2019
    Assignee: HELLA GMBH & CO. KGAA
    Inventors: Karsten Diekmann, Jürgen Heinrich, Andrew Ingle, Johannes Rosenberger, Thorsten Vehoff
  • Patent number: 10182533
    Abstract: A remote platform receives plant selection criteria and determines a plant selection based on the plant selection criteria. The plant selection criteria may include a plant preference, a budget preference, and garden parameters measured by sensors in a garden.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 22, 2019
    Assignee: GroGuru, Inc.
    Inventor: Farooq A. Anjum
  • Patent number: 10186509
    Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 22, 2019
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, James Jay McMahon, Ljubisa Dragoljub Stevanovic
  • Patent number: 10177208
    Abstract: A flexible display apparatus including a substrate including a flat surface portion and at least one curved surface portion, and a display including a first display region above the flat surface portion and a second display region above the at least one curved surface portion. The second display region includes a correcting layer including a first point and a second point apart from each other. The second point is farther away from the first display region than the first point. A thickness of the correcting layer at the second point is greater than a thickness of the correcting layer at the first point. The correcting layer includes a curved portion between the first point and the second point.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Youngseo Park
  • Patent number: 10172569
    Abstract: A system and method are provided that employ the variability of physiological waveforms to estimate the time to death after WLST, or time to inadequate organ perfusion. From the variability data one can derive an index subsequently used to determine the probability of death (or inadequate organ perfusion) within a given time frame in an automated fashion from bedside monitors in the intensive or post-anesthesia care unit. The resulting variability index can also be combined with the clinical variables used in other death prediction tools to enhance the performance and outcome when compared to existing models. In at least one implementation, variability monitoring at the bedside could be used to provide estimates of the probability that a patient will die within a certain time frame after WLST. These estimates could be used to reduce the distress of the patients' families, as well as optimize the use of resources surrounding donation.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: January 8, 2019
    Assignee: Ottawa Hospital Research Institute
    Inventors: Andrew J. E. Seely, Sonny Dhanani, Nathan B. Scales, Christophe L. Herry, Laura Hornby, Timothy O. Ramsay, Amanda S. Van Beinum
  • Patent number: 10163945
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 25, 2018
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
  • Patent number: 10163631
    Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chung Su, Ching-Yu Chang
  • Patent number: 10157974
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a first insulating film formed on the main surface, a first coil formed on the first insulating film, a second insulating film formed on the first coil and having a first main surface and first side surfaces continuous with the first main surface, a third insulating film formed on the first main surface of the second insulating film and having a second main surface and second side surfaces continuous with the second main surface, and a second coil formed on the second main surface of the third insulating film. The second insulating film and the third insulating film are formed as a laminated insulating film together. A thickness of the second coil is greater than a thickness of the first coil in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 18, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara