Abstract: An array substrate and a manufacturing method thereof, a display apparatus are disclosed. The manufacturing method of the array substrate includes a forming a conduction layer (20) for electrically connecting two adjacent pixel electrodes (104) upon forming of the pixel electrodes (104). The method further includes forming a photoresist layer (30) on a surface of a substrate with the conduction layer (20) formed thereon; through one exposure and development process, forming a first photoresist removed region (A) and a photoresist retained region (B). The first photoresist removed region (A) corresponds to a location of the conduction layer (20); the conduction layer (20) in the first photoresist removed region (A) is etched, to form a separating region (106) configured for avoiding electrical connection of pixel electrodes (104) of two adjacent pixel units; and within the separating region (106), a metal line that is non-electrically connected to adjacent two pixel electrodes (104) is formed.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer.

Abstract: Methods and compositions for depositing a monolayer onto a surface of a substrate are described. The method can include contacting the surface with a vapor phase comprising a carbene source, and reacting a carbene group from the carbene source with a functional group on the surface, to obtain a covalently bound monolayer on the surface of the substrate. The carbene source can be a diazirine compound. The functional group on the surface can be a C—H containing group, a Si—H containing group, among others, or combinations thereof. The method can further involve removing physisorbed molecules from the surface of the substrate.

Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.

Abstract: A light-emitting device comprises a first semiconductor layer; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises an adhesion layer on the second semiconductor layer, a conductive layer on the adhesion layer, and a bonding layer on the conductive layer, and wherein the electrode structure comprises a center region and an edge region, a thickness of each layer of the edge region of the electrode structure is smaller than that of the center region.

Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing methods, and a display device. A source electrode and a drain electrode of the TFT are each of a multi-layered structure including a metal layer and a metal barrier layer. An a-Si active layer of the TFT is covered with an etch stop layer, via-holes penetrating through the etch stop layer are provided at positions corresponding to the source electrode and the drain, and the source electrode and the drain electrode are connected to the a-Si active layer through the via-holes.

Abstract: A method for preparing CIGS absorber layers using CIGS nanoparticles on a substrate comprises one or more annealing steps that involve heating the CIGS nanoparticle film(s) to dry the film and possibly to fuse the CIGS nanoparticles together to form CIGS crystals. Generally, at least the final annealing step will induce particle fusion to form CIGS crystals. Reactive gas annealing has been found to facilitate the growth of larger grains in the resulting CIGS absorber layers and lead to improved photovoltaic performance of those layers. It is suspected that the presence of carbon in CIGS nanoparticle films hinders grain growth and limits the size of crystals which can be obtained in CIGS films upon annealing. It has been discovered that exposing the CIGS nanoparticle films to a reactive atmosphere containing sulfur can decrease the amount of carbon in the film, resulting in the growth of larger CIGS crystals upon annealing.

Abstract: A detection apparatus includes a plurality of conversion elements, an interlayer insulating layer, and a covering layer. Each of the plurality of conversion elements includes an electrode electrically connected to a corresponding one of a plurality of switching elements and a semiconductor layer disposed on the electrode. The interlayer insulating layer is disposed so as to cover the plurality of switching elements and composed of an organic material, and has a surface including a first region and a second region located outside the first region. The electrodes are disposed on the surface of the interlayer insulating layer in the first region. The covering layer is disposed on the surface of the interlayer insulating layer in the second region and composed of an inorganic material.

Abstract: A method for forming fins of a semiconductor device comprises forming a first hardmask on a substrate, a sacrificial layer on the first hardmask, and a second hardmask on the sacrificial layer. Portions of the second hardmask and the sacrificial layer are removed to form a mandrel. Spacers are formed adjacent to the sacrificial mandrel. A second sacrificial layer is deposited and portions of the second sacrificial layer are removed to expose portions of the spacers and the first hardmask. A first doped region and a second doped region are formed by annealing. The second hardmask and the sacrificial spacer are removed. Undoped portions of the sacrificial mandrel and the second sacrificial layer are removed to further expose portions of the first hardmask. Exposed portions of the first hardmask are removed to expose portions of the semiconductor substrate, and exposed portions of the semiconductor substrate are removed to form fins.

Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.

Abstract: To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid.

Abstract: A light-emitting element includes a semiconductor layered body comprising: an n-type semiconductor layer, and p-type semiconductor layer; an insulating film disposed on the semiconductor layered body and defining at least one p-side opening above the p-type semiconductor layer and a plurality of n-side openings exposing the n-type semiconductor layer; an n-side electrode disposed on the insulating film and comprising a plurality of first n-contact portions each electrically connected to the n-type semiconductor layer through one of the plurality of n-side openings; a p-side electrode electrically connected to the p-type semiconductor layer through the at least one p-side opening; a p-side post electrode disposed on the p-side electrode; and an n-side post electrode disposed on the n-side electrode. A total area of one or more first n-contact portions located on the second side is smaller than a total area of one or more first n-contact portion located on the first side.

Abstract: A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.

Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.

Abstract: Optical conversion layers based on semiconductor nanoparticles for use in lighting devices, and lighting devices including same. In various embodiments, spherical core/shell seeded nanoparticles (SNPs) or nanorod seeded nanoparticles (RSNPs) are used to form conversion layers with superior combinations of high optical density (OD), low re-absorbance and small FRET. In some embodiments, the SNPs or RSNPs form conversion layers without a host matrix. In some embodiments, the SNPs or RSNPs are embedded in a host matrix such as polymers or silicone. The conversion layers can be made extremely thin, while exhibiting the superior combinations of optical properties. Lighting devices including SNP or RSNP-based conversion layers exhibit energetically efficient superior prescribed color emission.

Abstract: A mask assembly and an apparatus and method of manufacturing a display apparatus. The mask assembly includes a mask frame, a plurality of mask sheets arranged on the mask frame, and a support frame arranged on the mask frame and having a portion that contacts and supports the mask sheets.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A method of fabricating electromagnetic radiation detection devices including: forming a first mask on a substrate; forming a structural layer on the substrate using the first mask; forming a metallic layer overlying the structural layer; removing the first mask; forming a second mask on the substrate, the second mask comprising mask openings; selectively patterning the metallic layer using the mask openings; and removing the second mask.