Abstract: A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.

Abstract: A fine interval coating member for a LED display and a coating method using the same are provided. The coating member includes column portions and row portions crossing the column portions, and holes between the column portions and the row portions. The body portion includes a material that is melted at a temperature higher than room temperature and that is cured at the room temperature.

Abstract: A method for determining an angle between a longitudinal axis of a first, leading component vehicle and a longitudinal axis of a second, trailing component vehicle. For at least one wheel axle or wheel axle group of the first, leading component vehicle a travel speed and/or an angular speed of the wheel axle or wheel axle group concerned is determined, and for at least one wheel axle or wheel axle group of the second, trailing component vehicle a travel speed and/or an angular speed of the wheel axle or wheel axle group concerned is determined. From the travel speeds and/or angular speeds determined for the wheel axles or wheel axle groups of the first, leading component vehicle and of the second, trailing component vehicle, the angle between the longitudinal axes of the first, leading component vehicle and the second, trailing component vehicle is then calculated.

Abstract: The invention concerns an optoelectronic device (40) comprising: a substrate (14); a first layer (42) covering the substrate, the first layer having a thickness greater than or equal to 15 nm and comprising a first material having an extinction coefficient greater than or equal to 3 for any wavelength between 380 and 650 nm; a second layer (18) covering and in contact with the first layer, the second layer having a thickness less than or equal to 20 nm and comprising a second material having a refraction index of between 1 and 3 and an extinction coefficient less than or equal to 1.5 or any wavelength between 380 and 650 nm; and conical or frustoconical wire semiconductor elements (24) each having a light-emitting diode stack (DEL), being in contact with the second layer.

Abstract: A light-emitting device comprises a plurality of light-emitting pillars separated from each other by a space, wherein each of the plurality of light-emitting pillars comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting pillars; a top electrode formed on the reflective layer and the plurality of light-emitting pillars; and a fill material formed between the reflective layer and the top electrode.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A light-emitting device, comprising: a substrate; a semiconductor stacking layer comprising a first type semiconductor layer on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises a bonding layer, a conductive layer, and a first barrier layer between the bonding layer and the conductive layer; wherein the conductive layer has higher standard oxidation potential than that of the bonding layer.

Abstract: The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench.

Abstract: A pixel definition layer and an OLED device are provided. The pixel definition layer includes a plurality of openings, the openings each being provided with bottom surface opening, a top surface opening and a side wall. The openings at least include a first opening defining a first pixel unit and a second opening defining a second pixel unit. The first opening is filled with a first pixel luminescent material, and the second opening is filled with a second pixel luminescent material. A decay rate of the first pixel luminescent material is lower than that of the second pixel luminescent material. The area of the bottom surface opening of the first opening is smaller than that of the bottom surface opening of the second opening. The side wall of the opening is provided with a pre-set reference surface. The pixel definition layer can be used for preparing an OLED device.

Abstract: De are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.

Abstract: An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Abstract: A semiconductor nanoparticle dispersion is provided. The semiconductor nanoparticle including a plurality of semiconductor nanoparticles having a radius equal to or larger than an exciton Bohr radius; and a solvent dispersed with the plurality of semiconductor nanoparticles.

Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.

Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.

Abstract: Methods for depositing materials on patterned substrates, and related devices, are generally provided. In some embodiments, a material is deposited on a patterned substrate. In certain embodiments, the substrate comprises a first portion with a material deposited on the first portion and a second portion of the substrate essentially free of the material. The methods described herein may be useful in fabricating sensors, circuits, tags, among other devices. In some cases, devices for determining analytes are also provided.

Abstract: A vehicle state estimation system and method uses an observer model to make cornering stiffness estimates from tire-based sensor data and vehicle-based sensor data throughout transient and non-transient operational maneuvers of a vehicle. A cornering stiffness identifier extracts transient-state cornering stiffness estimates from the cornering stiffness estimates made by the observer model and extracts from the transient-state cornering stiffness estimates an optimal transient-state cornering stiffness estimate having a substantially highest confidence measure for use by a vehicle control system.

Abstract: A method of evaluating a geometric parameter of a first fracture emanating from a first wellbore penetrating a subterranean formation is provided. The method includes the steps of forming the first fracture in fluid communication with the first wellbore; forming a second fracture in fluid communication with a second wellbore; measuring a first pressure change in the second wellbore in proximity to the first wellbore; and determining the geometric parameter of the first fracture using at least the measured first pressure change in an analysis which couples a solid mechanics equation and a pressure diffusion equation.