Abstract: Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a substrate and decreasing a width of the semiconductor fin. The method further includes forming a spacer layer on a surface of the substrate and forming a high dielectric constant layer on exposed surfaces of the semiconductor fin and the spacer layer. The method also includes forming a work function metal layer on the high dielectric constant layer. The method also includes removing portions of the work function metal layer and the high dielectric constant layer to expose portions of the spacer layer. A thickness of the remaining work function metal layer on sidewalls of the semiconductor fin is uniform.

Abstract: In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure. The TFE structure includes at least one dielectric layer and at least two barrier layers, and the TFE structure is formed over the OLED structure. The at least one dielectric layer is deposited by atomic layer deposition (ALD). Having the at least one dielectric layer formed by ALD in the TFE structure improves the barrier performance of the TFE structure.

Abstract: A sensor for measuring, for example, the pressure of a gas or other fluid comprising a glass substrate having an aperture defined therethrough. A semiconductor die defining a diaphragm is anodically bonded to the glass substrate such that the diaphragm is exposed via the aperture. At least one electrically conductive element in electrical communication with the semiconductor die is arranged on a surface of the glass substrate.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.

Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Abstract: A method for manufacturing semiconductor devices is provided. The method includes bonding a semiconductor element to a first surface of a planar lead frame, clamping a partial area of the lead frame to hold the lead frame and the semiconductor element in molding dies, and covering at least a part of the lead frame and the semiconductor element with a resin member by resin molding which fills the molding dies with resin. A thin-walled portion having a relative small thickness is previously formed on a shortest virtual line connecting a clamp area of the lead frame to an area where the semiconductor element is bonded.

Abstract: Techniques disclosed herein provide a method and fabrication structure for pitch reduction for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A hardmask is positioned first on an underlying layer or layers to be etched. A pattern of alternating materials is formed on the hardmask. One or more of the alternating materials can be preferentially removed relative to other materials to uncover a portion of the hardmask layer. The hardmask and the remaining lines of alternating material together form a combined etch mask defining sub-resolution features.

Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.

Abstract: A pixel array includes first signal lines, second signal lines, active elements, pixel electrodes, and selection lines. The second signal lines are intersected with and electrically insulated to the first signal lines to define pixel regions. The active element and the pixel electrode are disposed in the pixel regions. The active elements are electrically connected to the first signal lines and the second signal lines. The pixel electrodes are electrically connected to the active elements. The selection lines are disposed over the first signal lines and intersected with the first signal lines to form first intersections and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections and electrically insulated to the first signal lines at the second intersections. The selection lines and the pixel electrodes are leveled. The selection lines are electrically insulated to the second signal lines.

Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: Disclosed is an x-ray sensor having an active detector region including a plurality of detector diodes at a first side of the sensor, and with placement of the junction termination at a second opposite side of the sensor. Normally, this implies that the junction termination is moved from the top side where the active detector area is located to the bottom side of the sensor, allowing for full utilization of the active detector area at the top side with detector diodes to the very edge of the sensor.

Abstract: A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy anchor structure, with the dummy anchor located outside the outermost fin. The fins and dummy anchor define a trench, where the trench has a width dimension. The method continues with depositing a shallow trench isolation (STI) material into the trench and between the fins, where the STI material places uniform tension stresses on both sides of the individual fins.

Abstract: The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an element disposed on the substrate, and a cap enclosing the element. One of the substrate and the cap includes a groove, the other of the substrate and the cap includes a protrusion engaging with the groove. A first metal layer and a second metal layer form a metallic bond with each other in a space between the groove and the protrusion.