Patents Examined by Caleen Sullivan
  • Patent number: 10163682
    Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Soitec
    Inventors: C├ędric Malaquin, Ludovic Ecarnot, Damien Parissi
  • Patent number: 10163914
    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaoqiang Zhang, Hui Zang, Ratheesh R. Thankalekshmi, Randy W. Mann
  • Patent number: 10164056
    Abstract: Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a substrate and decreasing a width of the semiconductor fin. The method further includes forming a spacer layer on a surface of the substrate and forming a high dielectric constant layer on exposed surfaces of the semiconductor fin and the spacer layer. The method also includes forming a work function metal layer on the high dielectric constant layer. The method also includes removing portions of the work function metal layer and the high dielectric constant layer to expose portions of the spacer layer. A thickness of the remaining work function metal layer on sidewalls of the semiconductor fin is uniform.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Heng Wu, Peng Xu
  • Patent number: 10158098
    Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure. The TFE structure includes at least one dielectric layer and at least two barrier layers, and the TFE structure is formed over the OLED structure. The at least one dielectric layer is deposited by atomic layer deposition (ALD). Having the at least one dielectric layer formed by ALD in the TFE structure improves the barrier performance of the TFE structure.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 18, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jrjyan Jerry Chen, Xiangxin Rui, Soo Young Choi
  • Patent number: 10144634
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 4, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
  • Patent number: 10144636
    Abstract: A sensor for measuring, for example, the pressure of a gas or other fluid comprising a glass substrate having an aperture defined therethrough. A semiconductor die defining a diaphragm is anodically bonded to the glass substrate such that the diaphragm is exposed via the aperture. At least one electrically conductive element in electrical communication with the semiconductor die is arranged on a surface of the glass substrate.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: December 4, 2018
    Assignee: MEAS Switzerland S.a.r.l.
    Inventors: Jean-Francois le Neal, Predrag Drljaca
  • Patent number: 10141424
    Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, IBM CORPORATION
    Inventors: Remi Coquand, Emmanuel Augendre, Nicolas Loubet, Shay Reboh
  • Patent number: 10134790
    Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Wu, Chun-Chih Lin, Jian-Shin Tsai, Min-Hui Lin, Wen-Shan Chang, Yi-Ming Lin, Chao-Ching Chang, C. H. Chen, Chin-Szu Lee, Y. T. Tsai
  • Patent number: 10134893
    Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10134874
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10128242
    Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 10115889
    Abstract: A method for manufacturing semiconductor devices is provided. The method includes bonding a semiconductor element to a first surface of a planar lead frame, clamping a partial area of the lead frame to hold the lead frame and the semiconductor element in molding dies, and covering at least a part of the lead frame and the semiconductor element with a resin member by resin molding which fills the molding dies with resin. A thin-walled portion having a relative small thickness is previously formed on a shortest virtual line connecting a clamp area of the lead frame to an area where the semiconductor element is bonded.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 30, 2018
    Assignees: DENSO CORPORATION, TDK-MICRONAS GMBH
    Inventors: Toshiyuki Koumori, Yoshiyuki Kono, Tomoyuki Takiguchi, Yoshinori Inuzuka, Akitoshi Mizutani, Seiji Nishimoto, Camillo Pilla
  • Patent number: 10103032
    Abstract: Techniques disclosed herein provide a method and fabrication structure for pitch reduction for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A hardmask is positioned first on an underlying layer or layers to be etched. A pattern of alternating materials is formed on the hardmask. One or more of the alternating materials can be preferentially removed relative to other materials to uncover a portion of the hardmask layer. The hardmask and the remaining lines of alternating material together form a combined etch mask defining sub-resolution features.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 16, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 10096626
    Abstract: A pixel array includes first signal lines, second signal lines, active elements, pixel electrodes, and selection lines. The second signal lines are intersected with and electrically insulated to the first signal lines to define pixel regions. The active element and the pixel electrode are disposed in the pixel regions. The active elements are electrically connected to the first signal lines and the second signal lines. The pixel electrodes are electrically connected to the active elements. The selection lines are disposed over the first signal lines and intersected with the first signal lines to form first intersections and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections and electrically insulated to the first signal lines at the second intersections. The selection lines and the pixel electrodes are leveled. The selection lines are electrically insulated to the second signal lines.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 9, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Ni-Yeh Wu, Po-Chun Chuang, Pei-Lin Huang
  • Patent number: 10096542
    Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 9, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Cheng Lee, Yuan-Chang Su
  • Patent number: 10083997
    Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sanghoon Kim
  • Patent number: 10079174
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10074685
    Abstract: Disclosed is an x-ray sensor having an active detector region including a plurality of detector diodes at a first side of the sensor, and with placement of the junction termination at a second opposite side of the sensor. Normally, this implies that the junction termination is moved from the top side where the active detector area is located to the bottom side of the sensor, allowing for full utilization of the active detector area at the top side with detector diodes to the very edge of the sensor.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: September 11, 2018
    Assignee: PRISMATIC SENSORS AB
    Inventors: Mietek Bakowski Holtryd, Mats Danielsson, Cheng Xu
  • Patent number: 10068807
    Abstract: A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy anchor structure, with the dummy anchor located outside the outermost fin. The fins and dummy anchor define a trench, where the trench has a width dimension. The method continues with depositing a shallow trench isolation (STI) material into the trench and between the fins, where the STI material places uniform tension stresses on both sides of the individual fins.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Junli Wang, Peng Xu, Chen Zhang
  • Patent number: 10068820
    Abstract: The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an element disposed on the substrate, and a cap enclosing the element. One of the substrate and the cap includes a groove, the other of the substrate and the cap includes a protrusion engaging with the groove. A first metal layer and a second metal layer form a metallic bond with each other in a space between the groove and the protrusion.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Pil Joong Kang, Kwang Su Kim, Ji Hye Nam, Jeong Il Lee, Jong Hyeong Song, Yun Sung Kang, Seung Joo Shin, Nam Jung Lee