Patents Examined by Caleen Sullivan
  • Patent number: 9911809
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuichiro Sasaki, Bong Soo Kim, Tae Gon Kim, Yoshiya Moriyama, Seung Hyun Song, Alexander Schmidt, Abraham Yoo, Heung Soon Lee, Kyung In Choi
  • Patent number: 9908775
    Abstract: A transfer method, manufacturing method, device and electronic apparatus of MEMS. The method for MEMS transfer, comprising: depositing a laser-absorbing layer on a first surface of a laser-transparent carrier; forming a MEMS structure on the laser-absorbing layer; attaching the MEMS structure to a receiver; and performing a laser lift-off from the side of the carrier, to remove the carrier. A transfer of high-quality MEMS structure can be achieved in a simple, low cost manner.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: March 6, 2018
    Assignee: Goertek Inc.
    Inventors: Quanbo Zou, Zhe Wang
  • Patent number: 9905646
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsz-Mei Kwok, Ming-Hua Yu, Chii-Horng Li
  • Patent number: 9899288
    Abstract: A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the second die in a direction that is parallel to a sidewall of the first die. A molding compound extends along sidewalls of the first die and the second die, where at least a portion of a top surface of the molding compound includes an inclined surface. A polymer layer contacts the top surface of the molding compound, the top surface of the first die, and the top surface of the second die. A top surface of the polymer layer is substantially level. A first conductive feature is in the polymer layer, where the first conductive feature is electrically connected to the first die.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Tsung-Hsien Chiang, Guan-Yu Chen, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
  • Patent number: 9899354
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 9893166
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9892955
    Abstract: This substrate holding/rotating device includes an opening magnet forming a predetermined magnetic field generation region through which each movable pin rotating in response to rotation of the rotary table is capable of passing, the magnetic field generation region disposed so as to be eccentric with respect to a rotation direction of the rotary table and so as to allow only driving magnets corresponding to part of the plurality of movable pins to pass through the magnetic field generation region, the opening magnet giving a repulsive force or an attractive force to the driving magnet of the movable pin passing through the magnetic field generation region, the opening magnet generating a force that enables the support portion of the movable pin urged to the hold position by the urging unit to move toward the open position against an urging force of the urging unit.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: February 13, 2018
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Hiromichi Kaba, Akihiko Taki
  • Patent number: 9892946
    Abstract: A processing apparatus includes a spin coating chamber, an ultraviolet curing chamber, a transfer module and an enclosure. The transfer module is assigned with a plurality transfer destinations, in which two of the transfer destinations are respectively located within the spin coating chamber and the ultraviolet curing chamber. The transfer module, the spin coating chamber and the ultraviolet curing chamber are enclosed by the enclosure.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fang Cheng, Shao-Kuan Lee, Hai-Ching Chen
  • Patent number: 9893022
    Abstract: Circuits which self-destruct under radiation are provided. In one aspect, a method for creating a radiation-sensitive circuit is provided. The method includes the step of: connecting an integrated circuit to a power supply and to a ground in parallel with at least one dosimeter device, wherein the dosimeter device is configured to change from being an insulator to being a conductor under radiation. Radiation-sensitive circuits are also provided.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Fei Liu
  • Patent number: 9892977
    Abstract: A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsing Electronics Co., Ltd.
    Inventors: Sang Woo Pae, Hyun Chul Sagong, Jin Ju Kim, June Kyun Park
  • Patent number: 9893028
    Abstract: A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ming-Fa Chen, Yi-Hsiu Chen
  • Patent number: 9887084
    Abstract: A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an opening in the insulating layer, the opening exposing a surface of the substrate. The method also includes growing a nanowire over the exposed surface of the substrate, the nanowire extending out of the opening away from the substrate, the nanowire including a second semiconductor material different from the first semiconductor material. The method also includes laterally growing the second semiconductor material on exposed sidewalls of the nanowire.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Georgios Vellianitis
  • Patent number: 9881910
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 9875388
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 9871135
    Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: January 16, 2018
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Hongning Yang, Ronghua Zhu, Jiang-Kai Zuo
  • Patent number: 9865559
    Abstract: Provided is a method for manufacturing a stretchable wire, the method including removing a portion of a photoresist layer on a substrate to form a photoresist pattern comprising at least one pattern slit, applying a liquid-phase conductive material on the photoresist pattern to form a liquid-phase conductive structure in the pattern slit, forming a stretchable first insulating layer on the liquid-phase conductive structure, after removing the photoresist pattern, and separating the liquid-phase conductive structure and the first insulating layer from the substrate.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 9, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chan Woo Park, Jae Bon Koo, Bock Soon Na, Rae-Man Park, Ji-Young Oh, Sang Seok Lee, Soon-Won Jung
  • Patent number: 9865705
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9853084
    Abstract: A method of manufacturing an image sensor device includes, in a first manufacturing facility, forming a first set of patterned silicon, metal, and insulating layers on a glass substrate, forming an electrical and mechanical protection layer over the first set of patterned silicon, metal, and insulating layers, and, in a second manufacturing facility, removing the electrical and mechanical protection layer, forming a second set of patterned silicon, metal, and insulating layers over the first set of patterned silicon, metal, and insulating layers, forming a plurality of photosensors in communication with at least the second set of patterned silicon, metal, and insulating layers to form an unpassivated image sensor device, and forming a passivation layer over the unpassivated image sensor device. The materials used in the first set of layers and second set of layers can be completely or partially different.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 26, 2017
    Assignee: DPIX, LLC
    Inventors: Frank Caris, Shawn Michael O'Rourke, Byung-Kyu Park, Brian Rees
  • Patent number: 9852947
    Abstract: A method includes etching a dielectric layer to form an opening, with a component of a transistor being exposed through the opening. A spacer layer is formed, and includes a horizontal portion at a bottom of the opening, and a vertical portion in the opening. The vertical portion is on a sidewall of the dielectric layer. An isotropic etch is performed on the spacer layer to remove the horizontal portion, and the vertical portion remains after the isotropic etch. The remaining vertical portion forms a contact plug spacer. A conductive material is filled into the opening to form a contact plug.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting Ko, Kuang-Yuan Hsu
  • Patent number: 9847511
    Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure. The TFE structure includes at least one dielectric layer and at least two barrier layers, and the TFE structure is formed over the OLED structure. The at least one dielectric layer is deposited by atomic layer deposition (ALD). Having the at least one dielectric layer formed by ALD in the TFE structure improves the barrier performance of the TFE structure.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: December 19, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jrjyan Jerry Chen, Xiangxin Rui, Soo Young Choi