Patents Examined by Caleen Sullivan
  • Patent number: 10011742
    Abstract: Translucent multiphase adhesive comprising at least one continuous phase and dispersed domains, the at least one continuous phase having a refractive index of more than 1.45 and a permeation rate for water vapor of less than 100 g/m2, and the disperse domains being present in a size range of 0.1 ?m to 50 ?m and being included in a weight fraction of not more than 10 wt % in the adhesive, characterized in that the disperse domains are polymeric in nature and have a water vapor permeation rate of less than 100 g/m2d and a refractive index of less than 1.45.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 3, 2018
    Assignee: TESA SE
    Inventors: Klaus Keite-Telgenb├╝scher, Julia Rompf, Janika Stolze
  • Patent number: 10014232
    Abstract: The present invention provides a packaging shell and a power module having the same. The packaging shell mainly comprises an accommodating recess for receiving a substrate disposed with a plurality of electronic devices/components, so as to make the substrate be further assembled with a heat sink through the support of the packaging shell. Most importantly, in the present invention, the accommodating recess has a stepped surface for contacting with the substrate, and the stepped surface is a curve surface having a flatness difference. By such design, the compressional force generated when assembling the packaging shell, the heat sink and the system circuit board can be uniformly transmitted to substrate via the curve surface structure; such that the compressional force is avoid from being concentrated to a certain point on the substrate, and then the substrate is protected from being ruptured due to the action of the concentrated compressional force.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: July 3, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Xianming Wang, Shouyu Hong
  • Patent number: 10008478
    Abstract: The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 26, 2018
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Wanchun Ding
  • Patent number: 10008633
    Abstract: Disclosed are a light emitting diode and a lighting system having the same. The light emitting diode according to an embodiment may include a first electrode having a plurality of patterns formed on an upper surface thereof; a texture structure having a plurality of patterns corresponding to the plurality of patterns of the first electrode and configured to be in contact with at least one of the plurality of patterns of the first electrode; a first conductive semiconductor layer disposed on the texture structure; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; and a second electrode disposed on the second conductive semiconductor layer.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 26, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chan Keun Park, Hwan Hee Jeong
  • Patent number: 9997416
    Abstract: A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, a second contact trench over the second source/drain and adjacent the second gate structure, a first liner layer in the first trench positioned at a bottom part of the first trench, a second liner layer in the second trench and on the first liner layer in the first trench, a metallization layer in the first and second trenches on the second liner layer, and a first silicide contact between the first liner layer and the first source/drain and a second silicide contact between the second liner layer and the second source/drain.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu
  • Patent number: 9984788
    Abstract: There is provided a silver powder, which is able to obtain a conductive paste having a high thixotropic ratio and a high Casson yield value and which is able to form a conductive pattern having a low resistance, and a method for producing the same. An aliphatic amine such as hexadecylamine is added to a silver powder, the surface of which is coated with a fatty acid such as stearic acid, to be stirred and mixed to form the aliphatic amine on the outermost surface of the silver powder while allowing the fatty acid to react with the aliphatic amine to form an aliphatic amide such as hexadecanamide between the fatty acid and the aliphatic amine.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: May 29, 2018
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshiyuki Michiaki, Hiroshi Kamiga
  • Patent number: 9984882
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yong Li, Zhongshan Hong
  • Patent number: 9984887
    Abstract: A method of manufacturing a semiconductor device includes: forming a film on a substrate by time-divisionally and sequentially performing: (a) supplying a precursor gas to the substrate and causing precursor molecules, which are contained in the precursor gas and which contains a main element and ligands, to be adsorbed onto the substrate; (b) supplying a compound containing an electron withdrawing group to the substrate onto which the precursor molecules are adsorbed, and causing the compound containing the electron withdrawing group to be adsorbed to the ligands contained in the precursor molecules; and (c) supplying a reaction gas to the substrate onto which the precursor molecules and the compound containing the electron withdrawing group are adsorbed, causing the ligands and the compound containing the electron withdrawing group to be desorbed from the substrate, and causing the main element contained in the precursor molecules to react with the reaction gas.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Motomu Degai
  • Patent number: 9978590
    Abstract: A method of manufacturing an epitaxiable heat-dissipating substrate comprises the steps of (A) forming a roughened surface on a substrate made of a polycrystalline or amorphous material with a high thermal conductivity coefficient; (B) forming a flat layer on the roughened surface; and (C) forming a buffer layer on the flat layer. The flat layer reduces the surface roughness of the substrate, and then the buffer layer functions as a base for epitaxial growth, thereby being directly applicable to production of semiconductor devices which are flat and capable of isotropic epitaxial growth.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 22, 2018
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jian-Long Ruan, Shyh-Jer Huang, Hsin-Chieh Yu, Yang-Kuo Kuo
  • Patent number: 9972700
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9966363
    Abstract: A semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: May 8, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 9960038
    Abstract: Methods of forming microelectronic structure are provided. The methods comprise the formation of T-shaped structures using a controlled undercutting process, and the deposition of a selectively etchable composition into the undercut areas of the T-shaped structures. The T-shaped structures are subsequently removed to yield extremely small undercut-formed features that conform to the width and optionally the height of the undercut areas of the T-shaped structures. These methods can be combined with other conventional patterning methods to create structures having extremely small feature sizes regardless of the wavelength of light used for patterning.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 1, 2018
    Assignee: Brewer Science, Inc.
    Inventors: Carlton Ashley Washburn, James E. Lamb, III, Nickolas L. Brakensiek, Qin Lin, Yubao Wang, Vandana Krishnamurthy, Claudia Scott
  • Patent number: 9960086
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mira Park, Kwan-Yong Lim, Steven Bentley, Amitabh Jain
  • Patent number: 9953827
    Abstract: A method of fabricating a semiconductor device including an interlayer insulating layer and interconnections is provided. An interlayer insulating layer is formed on a substrate. An opening is formed in the interlayer insulating layer. A degassing process is performed by irradiating the interlayer insulating layer having the opening with microwaves. A K-value recovery process is performed by irradiating the interlayer insulating layer having the opening with UV light. A conductive layer is formed in the opening. The degassing process and the K-value recovery process are performed as an in-situ process.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woochoel Noh, Wonkyu Han, Hyeoksang Oh, Naein Lee, Gyeongyun Han
  • Patent number: 9954355
    Abstract: A transient voltage suppressor (TVS) apparatus includes a plurality of input/output (I/O) pins, a plurality of ground pins, and a substrate. The substrate includes a plurality of division parts and a carrier part. The carrier part carries a chip. The division parts are disposed between each of the I/O pins and the ground pins. The chip is electrically connected to the I/O pins and the ground pins, and the division parts are electrically insulated from the I/O pins and the ground pins.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 24, 2018
    Assignee: UBIQ Semiconductor Corp.
    Inventor: Chih-Hao Chen
  • Patent number: 9946162
    Abstract: An exposure method for exposing a mask pattern, which includes plural types of patterns, with a high throughput and optimal illumination conditions for each type of pattern. The method includes guiding light from a first spatial light modulator illuminated with pulse lights of illumination light to a second spatial light modulator and exposing a wafer with light from the second spatial light modulator, accompanied by: controlling a conversion state of the second spatial light modulator including a plurality of second mirror elements; and controlling a conversion state of the first spatial light modulator including a plurality of first mirror elements to control intensity distribution of the illumination light on a predetermined plane between the first spatial light modulator and the second spatial light modulator.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: April 17, 2018
    Assignee: Nikon Corporation
    Inventor: Soichi Owa
  • Patent number: 9941200
    Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 9938457
    Abstract: Methods for fabricating coated semiconductor elements are presented. The methods include the steps of combining a phosphor of formula I and a polymer binder to form a composite material, providing a semiconductor wafer including IniGajAlkN, wherein 0?i; 0?j; 0?k, and a sum of i, j and k is equal to 1, coating the composite material on a surface of the semiconductor wafer to form a coated semiconductor wafer, and dicing the coated semiconductor wafer using a cutting fluid apparatus to form one or more coated semiconductor elements. A cutting fluid of the cutting fluid apparatus includes a C1-C20 alcohol, a C1-C20 ketone, a C1-C20 acetate compound, acetic acid, oleic acid, carboxylic acid, a source of A, silicic acid, or a combination thereof.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 10, 2018
    Assignee: General Electric Company
    Inventors: Digamber Gurudas Porob, James Edward Murphy, Florencio Garcia, Srinivas Prasad Sista, Anant Achyut Setlur, William Winder Beers, Fangming Du
  • Patent number: 9941305
    Abstract: A pixel structure and a fabrication method thereof are provided, and the fabrication method includes steps as follows. A gate and a scan line connected to the gate electrode are formed on a substrate. An insulation layer is formed on the substrate and is patterned to form an opening corresponding to the gate electrode. A gate insulation layer is formed to cover the gate electrode and the scan line. A channel layer is formed on the gate insulation layer and is located in the opening. A first ohmic contact layer and a second ohmic contact layer are formed on the channel layer and are located in the opening. A source electrode, a drain electrode and a data line connected to the source electrode are formed on the first ohmic contact layer and the second ohmic contact layer. A first electrode is formed and is electrically connected to the drain electrode.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 10, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Chi-Ho Chang
  • Patent number: 9929292
    Abstract: A quantum cascade detector includes a semiconductor substrate; an active layer having a cascade structure; a lower cladding layer provided between the active layer and the substrate and having a lower refractive index than the active layer; a lower metal layer provided between the lower cladding layer and the substrate; an upper cladding layer provided on an opposite side to the substrate with respect to the active layer and having a lower refractive index than the active layer; and an upper metal layer provided on an opposite side to the active layer with respect to the upper cladding layer. A first end face being in a waveguide direction in a waveguide structure with the active layer, lower cladding layer, and upper cladding layer is an entrance surface for light to be detected.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 27, 2018
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tatsuo Dougakiuchi, Akio Ito, Tadataka Edamura, Kazuue Fujita