Patents Examined by Calvin Y Choi
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Patent number: 11876143Abstract: Provided is a terahertz light source device including an antenna, a plurality of wire electrodes configured to connect the antenna to a power source, a capacitor connected to the wire electrodes between the antenna and the power source, and a plurality of resonance tunneling diodes connected to the wire electrodes between the capacitor and the antenna, and configured to generate a terahertz wave by coupling with the capacitor as a parallel resonance circuit with respect to the power source.Type: GrantFiled: October 28, 2021Date of Patent: January 16, 2024Assignee: Electronics and Telecommunications Research InstituteInventors: Kiwon Moon, Kyung Hyun Park, Dong Woo Park, Jun-Hwan Shin, Eui Su Lee, Hyun Soo Kim, Il Min Lee
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Patent number: 11870002Abstract: According to embodiments provided herein, the performance of photovoltaic device can be improved by rapidly heating an absorber layer of a device in open-circuit to a high temperature for a short period of time followed by rapid quenching. The rapid heating may be accomplished by one or more pulses of high intensity electromagnetic energy. The energy may be visible light. The energy may be absorbed primarily in the absorber layer, such that the absorber layer is preferentially heated, promoting chemical reactions of dopant complexes. The dopant chemical reactions disrupt compensating defect complexes that have formed in the device, and regenerate active carriers.Type: GrantFiled: May 13, 2021Date of Patent: January 9, 2024Assignee: First Solar, Inc.Inventors: Dmitry Krasikov, Sachit Grover, Igor Sankin
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Patent number: 11864387Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.Type: GrantFiled: December 16, 2022Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Lifang Xu, Indra V. Chary, Justin B. Dorhout, Jian Li, Haitao Liu, Paolo Tessariol
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Patent number: 11862643Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.Type: GrantFiled: August 9, 2021Date of Patent: January 2, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toshinari Sasaki, Junichiro Sakata, Masashi Tsubuku
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Patent number: 11854902Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.Type: GrantFiled: July 20, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11848356Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.Type: GrantFiled: June 30, 2021Date of Patent: December 19, 2023Assignee: ATOMERA INCORPORATEDInventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
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Patent number: 11837634Abstract: A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.Type: GrantFiled: June 30, 2021Date of Patent: December 5, 2023Assignee: ATOMERA INCORPORATEDInventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
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Patent number: 11823999Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.Type: GrantFiled: October 1, 2021Date of Patent: November 21, 2023Assignee: SK hynix Inc.Inventors: Hae Chan Park, Jang Won Kim, Jae Taek Kim
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Patent number: 11804557Abstract: A high efficiency configuration for a solar cell module comprises solar cells arranged in an overlapping shingled manner and conductively bonded to each other in their overlapping regions to form super cells, which may be arranged to efficiently use the area of the solar module.Type: GrantFiled: September 28, 2021Date of Patent: October 31, 2023Assignee: MAXEON SOLAR PTE. LTD.Inventors: Yafu Lin, Benjamin Francois
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Patent number: 11796866Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: September 21, 2022Date of Patent: October 24, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof
Patent number: 11791265Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.Type: GrantFiled: March 14, 2022Date of Patent: October 17, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu -
Patent number: 11791357Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.Type: GrantFiled: August 4, 2021Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
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Patent number: 11785759Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.Type: GrantFiled: August 24, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
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Patent number: 11785776Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.Type: GrantFiled: September 14, 2022Date of Patent: October 10, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
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Patent number: 11784265Abstract: Disclosed are a mercury cadmium telluride-black phosphorus van der Waals heterojunction infrared polarization detector and a preparation method thereof. The structure of the detector from bottom to top comprises a substrate, a mercury cadmium telluride material, an insulating layer, a two-dimensional semiconductor black phosphorus, and metal electrodes.Type: GrantFiled: January 26, 2022Date of Patent: October 10, 2023Assignee: Shanghai Institute of Technical Physics Chinese Academy of SciencesInventors: Xudong Wang, Hanxue Jiao, Yan Chen, Jianlu Wang, Xiangjian Meng, Hong Shen, Tie Lin, Junhao Chu
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Patent number: 11784174Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a first die, a bumping structure, and a second die. The first die is on a carrier. The bumping structure is over the first die. The bumping structure includes a light-transmitting portion and a light-blocking portion embedded in the light-transmitting portion. The second die is electrically connected to the carrier. The light-blocking portion of the bumping structure is free from covering the second die.Type: GrantFiled: February 4, 2021Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Ying-Chung Chen
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Patent number: 11769843Abstract: A photonic module and a method of making same, the module having one or more optoelectronic chips, such as a laser diode typically having six sides, with each optoelectronic chip having two opposing sides (a first side and a second side) abutting and electrically connected to metal regions (preferably electro-formed), the two metal regions are physically distinct and electrically separate from each other, the two electro-formed metal regions serving, in use, as heat spreaders for conducting heat away from the optoelectronic chip.Type: GrantFiled: May 29, 2020Date of Patent: September 26, 2023Assignee: HRL LABORATORIES, LLCInventors: Daniel Yap, Florian G. Herrault, Christopher S. Roper, Partia Naghibi
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Patent number: 11769814Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.Type: GrantFiled: June 27, 2019Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Kevin L. Lin, Tristan Tronic
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Patent number: 11764325Abstract: Mercury cadmium telluride (MCT) dual band photodiode elements are described that include an n-type barrier region interposed between first and second p-type regions. The first p-type region is arranged to absorb different IR wavelengths to the second p-type region in order that the photodiode element can sense two IR bands. A portion of the second p-type region is type converted using ion-beam milling to produce a n-type region that interfaces with the second p-type region and the n-type barrier region.Type: GrantFiled: September 27, 2022Date of Patent: September 19, 2023Assignee: LEONARDO UK LTDInventors: Les Hipwood, Sudesh Bains
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Patent number: 11742450Abstract: An electro-optically controlled active-matrix system comprises a system substrate, row wires extending in a row direction disposed on the system substrate, a row controller providing a row electrical signal to each row wire, column light-pipes extending in a column direction disposed on the system substrate, a column controller providing a column optical signal to each column light-pipe, and pixels disposed over the system substrate. Each pixel can comprise a pixel circuit that is uniquely responsive to a row wire and to a column light-pipe, the pixel circuit receiving the row electrical signal from the row wire and receiving the column optical signal from the column light-pipe. In some embodiments, column wires carrying column electrical signals extend in a column direction over the system substrate and the pixel circuit is capacitively coupled to the row wire, the column wire, or both.Type: GrantFiled: August 31, 2020Date of Patent: August 29, 2023Assignee: X Display Company Technology LimitedInventors: Christopher Andrew Bower, Matthew Alexander Meitl, Robert R. Rotzoll, Ronald S. Cok