Abstract: A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

Abstract: Provided is an AlGaN unipolar carrier solar-blind ultraviolet detector that is based on the AlGaN polarization effect and that uses the double heterojunction of the p-AlzGa1-zN/i-AlyGa1-yN/n-AlxGa1-xN (0.45=<x,z<y) as the main structure of the detector. It makes full use of the polarization built-in electric field pointing from n-type AlGaN to p-type AlGaN to enhance the electric field strength of the i-type absorption region and enhance the efficiency of carrier absorption and separation. At the same time, the valence band step of the p-AlzGa1-zN/i-AlyGa1-yN heterojunction is used to effectively restrict holes from entering the absorption region to recombine with electrons, thereby increasing the carrier lifetime. Furthermore, during device manufacturing the structure is such designed that makes it difficult for photo-generated holes to participate in the photoconductivity so as to realize unipolar conduction of electrons, thereby obtaining a high response speed and high gain current.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.

Abstract: An optical sensor structure is provided. The optical sensor structure includes a substrate, a light sensing unit, a peripheral wall, and a reflective layer. The substrate includes a plurality of metal pads. The light sensing unit is disposed on the substrate and electrically connected to the plurality of metal pads. The peripheral wall is disposed on the substrate, and the peripheral wall and the substrate define an accommodating space. The metal pads and the light sensing unit are positioned in the accommodating space. The reflective layer is disposed in the accommodating space and surrounds the light sensing unit.

Abstract: A light sensing device includes a substrate, a gate electrode, a shielding electrode, a insulating layer, a semiconductor layer, a source electrode, and a drain electrode. The gate electrode and the shielding electrode are disposed over the substrate and spaced apart from each other. The insulating layer is disposed over the gate electrode and the shielding electrode. The semiconductor layer is disposed over the insulating layer. The source and drain electrodes are respectively connected to the semiconductor layer, and the semiconductor layer has a channel region between the source and drain electrodes. The channel region is divided into a first region adjacent to the drain electrode and overlapping the gate electrode and a second region adjacent to the source electrode and not overlapping the gate electrode, and the second region partially overlaps the shielding electrode.

Abstract: Mercury cadmium telluride (MCT) dual band photodiode elements are described that include an n-type barrier region interposed between first and second p-type regions. The first p-type region is arranged to absorb different IR wavelengths to the second p-type region in order that the photodiode element can sense two IR bands. A portion of the second p-type region is type converted using ion-beam milling to produce a n-type region that interfaces with the second p-type region and the n-type barrier region.

Abstract: A semiconductor light-receiving element, includes: a semiconductor substrate; a high-concentration layer of a first conductivity type formed on the semiconductor substrate; a low-concentration layer of the first conductivity type formed on the high-concentration layer of the first conductivity type and in contact with the high-concentration layer of the first conductivity type; a low-concentration layer of a second conductivity type configured to form a PN junction interface together with the low-concentration layer of the first conductivity type; and a high-concentration layer of the second conductivity type formed on the low-concentration layer of the second conductivity type and in contact with the low-concentration layer of the second conductivity type. The low-concentration layers have a carrier concentration of less than 1×1016/cm3. The high-concentration layers have a carrier concentration of 1×1017/cm3 or more.

Abstract: Photo-detection device (100) including a semiconductor substrate (110) made of CdxHg1-xTe, with an N-doped region (120), a P-doped region (130), and a concentrated casing (150) only located in the P-doped region and having an average cadmium concentration greater than the average cadmium concentration in the N-doped region. According to the invention, the concentrated casing (150) has a cadmium concentration gradient, defining therein at least one intermediate gap zone (151) and at least one high gap zone (152), and the intermediate gap zone (151) is in direct physical contact with an electrical contact block (170). A significant reduction in the dark current and an optimal charge carrier collection are thus combined.

Abstract: An electronic device comprises plural first substrates, plural photoelectric structures, a third substrate, plural driving units, plural conductive layers and plural first conductive structures. The first substrates are arranged in coplanar in a first direction. The photoelectric structures are arranged in coplanar in the first direction and disposed on the first substrate. Each photoelectric structure has a second substrate, a signal layer and a photoelectric component. The photoelectric component is electrically connected to the signal line of the signal layer. One of the photoelectric structures straddles two adjacent first substrates. The third substrate is connected to the first substrate or the photoelectric structure. The driving units are distributed on the first substrate or the photoelectric structure, and the driving units correspondingly drive the photoelectric components of the photoelectric structures.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

Abstract: A light emitting diode package including: a housing, wherein the housing has a first axis defined as a width (w), and a second axis defined as a height (h); a lead frame associated with the housing, wherein the lead frame includes a first electrode and a second electrode; wherein the first electrode and the second electrode are spaced apart from each other to define an inter-digit region therebetween, wherein the inter-digit region comprises a length (l) that is offset (e.g., not parallel) relative to the width and/or height of the housing.

Abstract: A sensor package array, a method of manufacturing the same, and a sensor package structure are provided. The method of manufacturing a sensor package array including: disposing a plurality of sensors on a substrate sequentially in an array; electrically connecting the plurality of sensors to the substrate; disposing a plastic shield on the substrate, so as to form a plurality of channels and a plurality of accommodating grooves among the plastic shield, the substrate, and the plurality of sensors; and filling a sealing material in the plurality of accommodating grooves, through the plurality of channels.

Abstract: A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.

Abstract: A light-emitting device comprises a semiconductor layer; a pad electrode comprising a periphery disposed on the semiconductor layer; a finger electrode connected to the pad electrode, wherein the finger electrode comprises a first portion extended from the periphery of the pad electrode and a second portion connected to the first portion; and a plurality of first current blocking regions formed on the semiconductor layer, separated from the pad electrode and formed under the finger electrode, wherein one of the plurality of first current blocking regions is most close to the pad electrode and is separated from the pad electrode by a first distance, adjacent two of others of the plurality of first current blocking regions are separated from each other by a second distance, and the first distance is longer than the second distance.

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly packaged LEDs with light-altering materials are disclosed. A light-altering material is provided in particular configurations within an LED package to redirect light from an LED chip within the LED package and contribute to a desired emission pattern of the LED package. The light-altering material may also block light from the LED chip from escaping in a non-desirable direction, such as large or wide angle emissions. The light-altering material may be arranged on a lumiphoric material adjacent to the LED chip in various configurations. The LED package may include an encapsulant on the light-altering material and the lumiphoric material.

Abstract: An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.