Abstract: A light-emitting device comprises a semiconductor stack; a pad electrode comprising a periphery disposed on the semiconductor stack; and a finger electrode connected to the pad electrode, wherein the finger electrode comprises a first portion extended from the periphery of the pad electrode and a second portion away from the pad electrode, the first portion comprises a first side and a second side, the first side is opposite to the second side, the first side comprises a first arc having a first curvature radius, and the first curvature radius is larger than 10 ?m.

Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.

Abstract: Provided is a radiation detecting element that has high adhesion between electrode portions and a substrate and does not suffer from performance failures due to insufficient insulation between the electrode portions, even if a distance between the electrode portions is narrower in order to obtain a high-definition radiation drawn image. The radiation detecting element includes: a plurality of electrode portions; and an insulating portion provided between the electrode portions on a surface of a substrate made of a compound semiconductor crystal containing cadmium telluride or cadmium zinc telluride, wherein an intermediate layer containing tellurium oxide is present between each of the electrode portions and the substrate, and wherein tellurium oxide is present on an upper portion of the insulating portion, and the tellurium oxide on the upper portion of the insulating portion has a maximum thickness of 30 nm or less.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

Abstract: Shockley-Read-Hall (SRH) generation and/or recombination in heterojunction devices is suppressed by unconventional doping at or near the heterointerface. The effect of this doping is to shift SRH generation and/or recombination preferentially into the wider band gap material of the heterojunction. This reduces total SRH generation and/or recombination in the device by decreasing the intrinsic carrier concentration ni at locations where most of the SRH generation and/or recombination occurs. The physical basis for this effect is that the SRH generation and/or recombination rate tends to decrease as ni around the depletion region decreases, so decreasing the effective ni in this manner is a way to decrease SRH recombination.

Abstract: Provided is an infrared detecting device with a high SNR. The infrared detecting device includes: a semiconductor substrate 10; a first layer 21 having a first conductivity type on the semiconductor substrate; a light receiving layer 22 on the first layer; and a second layer 23 having a second conductivity type on the light receiving layer. A part of the first layer, the light receiving layer, and the second layer form a mesa structure, the light receiving layer contains AlxIn1-xSb (0.05<x<0.18), and at least a part of side surfaces of the mesa structure are covered with a protective layer, and part of the protective layer that is in contact with side surfaces of the light receiving layer is made of silicon nitride.

Abstract: Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

Abstract: A package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.

Abstract: A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

Abstract: Disclosed is a photosensitive component, including: an intrinsic layer; a first doped layer provided on a light incident side of the intrinsic layer; and a second doped layer provided on a light exit side of the intrinsic layer; the intrinsic layer, the first doped layer and the second doped layer are all doped with a dopant, and silicon ions are injected into the intrinsic layer, the first doped layer and the second doped layer. An X-ray detector and a display device are further disclosed.

Abstract: An X-ray device including a sensing panel is provided. The sensing panel includes a first pixel and a second pixel. The second pixel is disposed adjacent to the first pixel in a top view direction. The first pixel includes a first photoelectric conversion layer. The second pixel includes a second photoelectric conversion layer. The first photoelectric conversion layer and the second photoelectric conversion layer belong to different layers.

Abstract: There is provided a technique that includes filling a concave portion formed on a surface of a substrate with a first film and a second film by performing: (a) forming the first film having a hollow portion using a first precursor so as to fill the concave portion formed on the surface of the substrate; (b) etching a portion of the first film which makes contact with the hollow portion, using an etching agent; and (c) forming the second film on the first film of which the portion is etched, using a second precursor, wherein (b) includes performing, a predetermined number of times: (b-1) modifying a portion of the first film using a modifying agent; and (b-2) selectively etching the modified portion of the first film using the etching agent.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.

Abstract: A vertical memory device includes first horizontal gate electrodes disposed on a substrate and spaced apart from each other in a first direction that is substantially perpendicular to an upper surface of the substrate. Each of the first horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. A vertical channel extends through the first horizontal gate electrodes in the first direction. A charge storage structure is disposed between the vertical channel and each of the first horizontal gate electrodes. A first vertical gate electrode extends through the first horizontal gate electrodes in the first direction. The first vertical gate electrode is electrically insulated from the first horizontal gate electrodes. A first horizontal channel is disposed at a portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode.

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: According to an embodiment, a self-powered sensor comprises at least one first layer emitting light in a preset wavelength band by receiving power from an outside, or receiving the emitted light reflected by an object, at least one second layer receiving light and generating a current, and a plurality of connectors each grown between two adjacent ones of the at least one first layer and the at least one second layer, the plurality of connectors transferring the generated current to the outside or transferring the power received from the outside to the at least one first layer and the at least one second layer.

Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer may be formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.

Abstract: The present technology relates to a light reception device and a distance measurement module whose characteristic can be improved. The light reception device includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first tap having a first voltage application portion and a first charge detection portion arranged around the first voltage application portion, and a second tap having a second voltage application portion and a second charge detection portion arranged around the second voltage application portion. Furthermore, the light reception device is configured such that a phase difference is detected using signals detected by the first tap and the second tap. The present technology can be applied, for example, to a light reception device that generates distance information, for example, by a ToF method, and so forth.

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.