Abstract: Discussed is an organic light emitting diode (OLED) lighting apparatus including a substrate; an auxiliary wiring disposed on the substrate; a protective layer configured to cover the auxiliary wiring; a first electrode disposed between the auxiliary wiring and the protective layer to be in direct contact with the auxiliary wiring, the first electrode including a first layer and a second layer, the first layer having a first resistance, and the second layer being configured to cover the first layer and the protective layer and having a second resistance higher than the first resistance; an organic light emitting layer disposed on the first electrode; and a second electrode disposed on the organic light emitting layer.

Abstract: An embodiment discloses a semiconductor device including a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; and a second electrode electrically connected with the second conductive semiconductor layer, and a semiconductor device package including the same. The second conductive semiconductor layer includes a first surface on which the second electrode is disposed. The second conductive semiconductor layer has a ratio of a second shortest distance W2, which is a distance from the first surface to a second point, to a first shortest distance W1, which is a distance from the first surface to a first point, (W2:W1) ranging from 1:1.25 to 1:100.

Abstract: A method for producing a component having a semiconductor body includes providing the semiconductor body including a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier including a carrier layer and a partly cured connecting layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer to form a solid composite, applying a molded body material on the composite carrier after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material.

Abstract: A manufacturing method of a display panel is provided and includes providing a substrate; and forming a buffer layer, a polysilicon layer, a gate electrode, an interlayer insulating layer, a first transparent electrode layer, a source electrode and drain electrode line, and a touch control line on the substrate in sequence. A masking process is omitted using a planarization layer as a photoresist layer of the interlayer insulating layer. One more masking process is omitted by forming the pixel electrode, the source electrode and drain electrode line and the touch control line in a same masking process.

Abstract: A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.

Abstract: A thin-film transistor (TFT), an array substrate, a manufacturing method thereof and a display device are provided. The TFT includes an active layer, a gate electrode, a first source/drain electrode and a second source/drain electrode. The active layer includes a first channel region and a second channel region, a first source/drain area between the first channel region and the second channel region, and a second source/drain area opposite to the first source/drain area through the first channel region or the second channel region. The gate electrode includes a first gate electrode and a second gate electrode which are respectively overlapped with the first channel region and the second channel region. The first source/drain electrode and the second source/drain electrode are respectively electrically connected with the first source/drain area and the second source/drain area of the active layer.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: An imaging device includes a semiconductor substrate having a first surface; a microlens located above the first surface of the semiconductor substrate; and one or more photoelectric converters located between the first surface of the semiconductor substrate and the microlens, each of the one or more photoelectric converters including a first electrode, a second electrode located closer to the microlens than the first electrode is, and a photoelectric conversion layer that is located between the first electrode and the second electrode and that converts light into electric charges, wherein a focal point of the microlens is located below a lowermost surface of the photoelectric conversion layer of a first photoelectric converter, the first photoelectric converter being located closest to the first surface of the semiconductor substrate among the one or more photoelectric converters.

Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.

Abstract: Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.

Abstract: A laser processing method for a wafer that is segmented by plural planned dividing lines set on a surface in a lattice manner uses a laser processing apparatus including a laser beam irradiation unit that irradiates, through a collecting lens, the wafer held by a chuck table, with plural laser beams formed by being oscillated by a laser beam oscillator and being split by a laser beam splitting unit. The method includes a processed groove forming step of irradiating the wafer with the plural laser beams along the planned dividing lines and forming a processed groove along the planned dividing lines. The plural laser beams split by the laser beam splitting unit are arranged in a line manner along a direction that is non-parallel to an extension direction of the planned dividing line irradiated with the plural laser beams.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

Abstract: A display device including a gate line, first and second data lines adjacent to each other in a first direction and crossing the gate line, a first transistor electrically connected to the gate line and the first data line, and a first pixel electrode electrically connected to the first transistor, in which the first pixel electrode includes a first sub-electrode and a second sub-electrode adjacent to each other in the first direction, the first sub-electrode includes a first longitudinal stem extending in a direction substantially parallel to the first data line and overlapping the first data line and a plurality of first branches connected to the first longitudinal stem, and the second sub-electrode includes a second longitudinal stem extending in a direction substantially parallel to the second data line and overlapping the second data line and a plurality of second branches connected to the second longitudinal stem.

Abstract: An apparatus includes a housing base and a circuit board. The housing base contains a cavity, a boss containing a mounting bore, and a support pad connected to the boss. The circuit board is positioned in the cavity so that an accelerometer carried by the circuit board is disposed directly above the support pad.

Abstract: A method is for making an optical detector device. The method may include forming a reflector layer carried by a substrate, forming a first dielectric layer over the reflector layer, and forming a graphene layer over the first dielectric layer and having a perforated pattern therein.

Abstract: A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.

Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.

Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.