Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A structure includes a metal layer and a plurality of interconnected unit cells forming a lattice contained at least partly within the metal layer, including at least a first unit cell formed of first interconnected graphene tubes, and a second unit cell formed of second interconnected graphene tubes, wherein the metal layer protrudes through holes within the lattice.

Abstract: In an example, a method may include removing a material from a structure to form an opening in the structure, exposing a residue, resulting from removing the material, to an alcohol gas to form a volatile compound, and removing the volatile compound by vaporization. The structure may be used in semiconductor devices, such as memory devices.

Abstract: A method for manufacturing a semiconductor device includes forming a SiN film on a substrate. Plasma treatment is applied to the SiN film using a He-containing gas.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: A method of making a thin film transistor, the method includes: providing a semiconductor layer; arranging a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure includes a single nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening; depositing a conductive film layer on the exposed surface using the nanowire structure as a mask, wherein the conductive film layer defines a nano-scaled channel, and the conductive film layer is divided into two regions, one region is used as a source electrode, and the other region is used as a drain electrode; forming an insulating layer on the semiconductor layer to cover the source electrode and the drain electrode, and locating a gate electrode on the insulating layer.

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

Abstract: A display apparatus includes a substrate including a display area where a plurality of pixels are provided and a non-display area surrounding the display area, an encapsulation layer including an inorganic layer and an organic layer and covering the display area, a dam disposed in the non-display area to surround the display area and to block a flow of the organic layer, a pad disposed in one edge of the non-display area and spaced apart from the dam in the non-display area, an auxiliary buffer layer spaced apart from the dam and disposed in the non-display area to overlap an end of the inorganic layer, a power auxiliary line disposed between the dam and the auxiliary buffer layer and electrically connected to the pad to receive a voltage from the pad, and a crack detection line spaced apart from the power auxiliary line and electrically connected to the pad.

Abstract: Provided is a semiconductor device manufacturing method which can suppress the occurrence of positional deviation or inclination of a semiconductor element when the semiconductor element is fixed so as to be sandwiched-between two insulating substrates. The semiconductor device manufacturing method includes: obtaining a laminated body in which a semiconductor element is temporarily adhered on a first electrode formed on a first insulating substrate with a first pre-sintering layer sandwiched therebetween; temporarily adhering the semiconductor element on a second electrode formed on a second insulating substrate with a second pre-sintering layer sandwiched therebetween, the second pre-sintering layer being provided on a side opposite to the first pre-sintering layer, to obtain a semiconductor device precursor; and simultaneously heating the first pre-sintering layer and the second pre-sintering layer, to bond the semiconductor element to the first electrode and the second electrode.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

Abstract: Embodiments of the present disclosure provide a flexible display panel, a method of manufacturing the flexible display panel, and a flexible display apparatus. The flexible display panel comprises: a reinforced insulating layer of an inorganic material, wherein the reinforced insulating layer comprises a reinforced region, and is formed with a reinforcing hole in the reinforced region; an organic material filled in the reinforcing hole; and at least one insulating film which is disposed on at least one of both sides of the reinforced insulating layer and which is in contact with the reinforced insulating layer at least in the reinforced region.

Abstract: A flexible array substrate includes an active area and a bending area. The bending area is adjacent to the active area. The bending area includes a protection layer and at least one signal line disposed on the base substrate. The protection layer is located on the at least one signal line at a side away from the base substrate. An orthographic projection of the protection layer on the base substrate has an overlapping region with an orthographic projection of the at least one signal line on the base substrate, the Young modulus of the protection layer is larger than or equal to the Young modulus of the at least one signal line.

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

Abstract: The present disclosure includes apparatuses and methods related to sublimation in forming a semiconductor. In an example, a method may include forming a sacrificial material in an opening of a structure, wherein the sacrificial material displaces a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to sub-atmospheric pressure.

Abstract: Forming a thermal interface material structure includes forming an assembly that includes a thermal interface material disposed between a first mating surface and a second mating surface. The first mating surface is associated with a module lid, and the second mating surface is associated with a heat sink. Protruding surface features are incorporated onto the first mating surface or the second mating surface. The process also includes compressing the assembly to form a thermal interface material structure. The thermal interface material structure includes the thermal interface material disposed within an interface defined by the first mating surface and the second mating surface. The protruding surface features protrude from the first mating surface or the second mating surface into selected areas of the interface to limit relative movement of the mating surfaces into the selected areas during thermal cycling to reduce thermal interface material migration out of the interface.

Abstract: Provided is a display device including an organic insulating layer; a pixel electrode on the organic insulating layer; a pixel defining layer configured to cover an edge of the pixel electrode, having an opening corresponding to the pixel electrode, the pixel defining layer including a first layer including an inorganic insulating material and a second layer having less light transmittance in a first wavelength band than the first layer; an intermediate layer on a portion of the pixel electrode exposed via the opening, and including an emission layer; and an opposite electrode on the intermediate layer.

Abstract: A method for manufacturing a lead frame including: punching a metal plate disposed on a die with a punch in a direction from the metal plate toward a die side to form a punched metal, the punched metal including at least one electrode, at least one hanger lead separated from the at least one electrode, and an outer frame connected to the at least one electrode and the at least one hanger lead; and stamping at least part of a corner of an end of the at least one hanger lead, the corner being on a side corresponding to the die side, with a vertically split mold to form at least one chamfered surface.

Abstract: An organic light emitting display (OLED) device includes a substrate having a display region and a peripheral region at least partially surrounding the display region. An insulating layer structure is disposed on the substrate within both the display region and the peripheral region. The insulating layer structure includes a groove in the peripheral region. A plurality of pixel structures is disposed in the display region on the insulating layer structure. A block structure is disposed in the peripheral region so as to at least partially overlap the groove of the insulating layer structure. The block structure at least partially fills the groove of the insulating layer structure.