Patents Examined by Candice Chan
  • Patent number: 10748801
    Abstract: According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 18, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gunther Mackh, Markus Brunnbauer, Adolf Koller, Jochen Mueller
  • Patent number: 10727209
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first element insulating part, and an insulating sealing member. The first semiconductor element includes a first semiconductor chip and a first chip electrode electrically connected to the first semiconductor chip. The first semiconductor chip has a first surface crossing a first direction, a second surface crossing the first direction and distant from the first surface, and a third surface between the first and second surfaces. The first chip electrode is disposed on the first surface. The first element insulating part includes a first portion and a second portion continuous to the first portion. The insulating sealing member includes a third portion and a fourth portion continuous to the third portion. The first portion is between the first surface and the third portion, and the second portion is between the third surface and the fourth portion.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiro Iguchi, Akiya Kimura, Akihiro Sasaki
  • Patent number: 10714689
    Abstract: A production method for an OLED panel includes forming on an upper face side of a transparent substrate, a layered body including a resin layer, a TFT layer, an OLED layer and a sealing layer including an organic sealing film, and then irradiating the resin layer being in contact with the transparent substrate with a laser beam to separate the transparent substrate and the layered body. In the production method, the resin layer includes a first region to be irradiated with a laser beam at a first intensity P1 and a second region to be irradiated with a laser beam at a second intensity P2 greater than the first intensity, the first region overlaps with the organic sealing film, and the second region does not overlap with the organic sealing film.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tetsunori Tanaka
  • Patent number: 10707290
    Abstract: Provided are a flexible display panel and a flexible display device, in which a non-display area surrounds a display area. A concave area protrudes along a direction away from interior of display area. A convex area has a folding axis parallel to a first edge. The non-display area includes a fan-out area, in which lead wires are provided. Each lead wire has a first end and a second end. There are signal traces each extending along a first direction provided in display area. The signal traces are electrically connected to first ends of lead wires. The convex area and concave area are arranged along a second direction. The second direction intersects first direction. A driving chip is included, which is a ball grid array package driving chip and is arranged in concave area where lead wires are away from first edge and electrically connected to second ends of lead wires.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 7, 2020
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Quanpeng Yu, Wenxin Jiang, Chuanli Leng, Zhenying Li, Xilie Li, Zhe Li, Conghui Liu
  • Patent number: 10672688
    Abstract: A semiconductor power device including a base plate, a ring frame disposed over the base plate, a semiconductor power die disposed on the base plate and surrounded by the ring frame, an input lead by way the semiconductor power die receives an input signal, wherein the input lead is disposed over a first portion of the ring frame, and an output lead by way an output signal generated by the semiconductor power die is sent to another device, wherein the output lead is disposed over a second portion of the ring frame. The ring frame may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The ring frame produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Integra Technologies, Inc.
    Inventor: William Veitschegger
  • Patent number: 10672685
    Abstract: A display device is disclosed, which includes: a substrate having a first surface and a second surface, wherein the first surface is opposite to the second surface; a first conductive element disposed on the first surface; a second conductive element disposed on the second surface; and a connecting element disposed in a through via of the substrate, wherein the connecting element electrically connects the first conductive element and the second conductive element; wherein the second conductive element has a first oxygen atomic concentration, the connecting element has a second oxygen atomic concentration, and the first oxygen atomic concentration is greater than the second oxygen atomic concentration.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 2, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Jui-Jen Yueh, Kuan-Feng Lee, Yuan-Lin Wu, Chandra Lius
  • Patent number: 10672856
    Abstract: A display device including a substrate, a display region, a periphery region outside of the display region, a terminal part arranged with a plurality of terminal electrodes in the periphery region, a wiring arranged between the display region and the terminal part, a plurality of inorganic insulation layers, and an organic insulation film arranged between the display region and the terminal part. At least one of the plurality of inorganic insulation layer extends between the display region and the terminal part and includes an opening part between the display region and the terminal part, the organic insulation film is arranged overlapping the opening part, the organic insulation film has a larger film thickness at a center part than an end part of the opening part, and the wiring is arranged along an upper surface of the organic insulation film.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 2, 2020
    Assignee: Japan Display Inc.
    Inventor: Masato Hiramatsu
  • Patent number: 10665482
    Abstract: A method for processing a plate-shaped workpiece having a division line and a metal member formed on the division line or in an area corresponding to the division line includes a holding step of holding the workpiece on a chuck table with the metal member oriented downward, a first cutting step of cutting the workpiece along the division line by using a first cutting blade, thereby forming a first cut groove having a bottom not reaching the metal member, and a second cutting step of cutting the workpiece along the first cut groove by using a second cutting blade, thereby forming a second cut groove fully cutting the workpiece along the division line so as to divide the metal member. The second cutting step includes supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 26, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10658539
    Abstract: A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 19, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Zhen Peng, Nathaniel Quitoriano, Marco Fiorentino
  • Patent number: 10658251
    Abstract: A process of forming an epitaxial substrate is disclosed, where the epitaxial substrate includes a nucleus forming layer made of aluminum nitride (AlN) grown on a substrate made of silicon carbide (SiC). The process includes steps of: (1) first measuring the first reflectivity R0 of a surface of the SiC substrate, (2) growing the nucleus forming layer made of AlN as measuring second reflectivity R1 of a grown surface of the AlN nucleus forming layer, and (3) ending the growth of the AlN nucleus forming layer when a ratio R1/R0 of the reflectivity enters a preset range.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 19, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS
    Inventor: Tadashi Watanabe
  • Patent number: 10651207
    Abstract: A display device may include a substrate; a plurality of signal lines on the substrate; a plurality of scan lines on the substrate, the scan lines crossing the signal lines; and a plurality of thin film transistors at crossing positions of the scan lines and the signal lines. The scan lines include some first scan lines and some second scan lines. Each of the second scan lines has an end connected to a load element.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 12, 2020
    Assignee: Japan Display Inc.
    Inventors: Daichi Hosokawa, Naoki Miyanaga, Masakatsu Kitani
  • Patent number: 10636917
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhihong Chen, Shu-Jen Han, Siyuranga O. Koswatta, Alberto Valdes Garcia
  • Patent number: 10629661
    Abstract: An embodiment of the present disclosure provides an organic light emitting diode array substrate, an organic light emitting diode display and a method for manufacturing the same. Specifically, the organic light emitting diode array substrate comprises a substrate; a reflecting layer provided on the substrate; a photoresist layer provided on the reflecting layer, and a pixel electrode layer provided on the photoresist layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Minghung Hsu
  • Patent number: 10615080
    Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul Sun, Myeong-Cheol Kim, Kyoung-Sub Shin
  • Patent number: 10607865
    Abstract: A method for processing a plate-shaped workpiece having a division line and a metal member formed on the division line or in an area corresponding to the division line includes a holding step of holding the plate-shaped workpiece on a chuck table where the metal member is exposed, a first cutting step of cutting the plate-shaped workpiece along the division line by using a first cutting blade after performing the holding step, thereby forming a first cut groove dividing the metal member, and a second cutting step of cutting the plate-shaped workpiece along the first cut groove by using a second cutting blade after performing the first cutting step, thereby forming a second cut groove fully cutting the plate-shaped workpiece. The first cutting step includes the step of supplying a cutting fluid containing an organic acid and an oxidizing agent to the plate-shaped workpiece.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 31, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10600862
    Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminals and including a drift region with dopants of a first conductivity type. An active region has at least one power cell extending at least partially into the semiconductor body, is electrically connected with the first load terminal and includes a part of the drift region. Each power cell includes a section of the drift region and is configured to conduct a load current between the terminals and to block a blocking voltage applied between the terminals. A chip edge laterally terminates the semiconductor body. A non-active termination structure arranged in between the chip edge and active region includes an ohmic layer. The ohmic layer is arranged above a surface of the semiconductor body, forms an ohmic connection between electrical potentials of the first and second load terminals, and is laterally structured along the ohmic connection.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Erich Griebl, Frank Wolter, Andreas Moser, Manfred Pfaffenlehner
  • Patent number: 10559671
    Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Choonghyun Lee, Alexander Reznicek, Christopher Waskiewicz
  • Patent number: 10558839
    Abstract: In some embodiments of the disclosed subject matter, a touch sensing pattern recognition array substrate, and related unit, sensor, apparatus, and fabricating method are provided. The sensing unit on the touch sensing pattern recognition array substrate comprises a thin film transistor part and a photosensitive part. The photosensitive part comprises an opaque electrode, a transparent electrode, and a photosensitive layer sandwiched by the opaque electrode and the transparent electrode. The thin film transistor part comprises a gate electrode connected with a scanning line, a source electrode connected with a signal line, and a drain electrode connected with the photosensitive layer of the photosensitive part.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 11, 2020
    Assignees: BOE Technology Group Co., Ltd., BEIJING BOE Optoelectronics Technology Co., Ltd.
    Inventors: Changfeng Li, Xue Dong, Haisheng Wang, Xiaochuan Chen, Yingming Liu, Shengji Yang, Xiaoliang Ding, Lei Wang, Rui Xu, Jingbo Xu, Hongbo Feng, Jiantao Liu, Yingzi Wang, Minqiang Yang
  • Patent number: 10559672
    Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Choonghyun Lee, Alexander Reznicek, Christopher Waskiewicz
  • Patent number: 10546946
    Abstract: Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaaki Shinohara