Abstract: A method of processing a plate-shaped workpiece that includes layered bodies containing metal which are formed in superposed relation to projected dicing lines includes the steps of holding the workpiece on a first holding table such that the layered bodies are exposed, thereafter, cutting the workpiece along the projected dicing lines with a cutting blade to form cut grooves that sever the layered bodies, thereafter, holding the workpiece on a second holding table such that a mask disposed in areas that are exclusive of the projected dicing lines is exposed, and thereafter, performing dry etching on the workpiece through the mask to sever the workpiece along the projected dicing lines. The step of cutting the workpiece includes the step of cutting the workpiece while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.

Abstract: A semiconductor device includes a substrate, electrical conductors and a passivation layer. Each of the electrical conductors includes a first portion through the substrate, and a second portion over the surface of the substrate and connected to the first portion. The passivation layer is over the surface of the substrate, wherein the passivation layer partially covers an edge of the second portion of each of the electrical conductors.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: A method of processing a plate-shaped workpiece that includes layered bodies containing metal which are formed in superposed relation to projected dicing lines, includes the steps of holding the workpiece on a holding table, and thereafter, cutting the workpiece along the projected dicing lines with an annular cutting blade, thereby separating the layered bodies. The cutting blade has a slit which is open at an outer peripheral edge thereof. The step of cutting the workpiece includes the step of cutting the workpiece while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.

Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.

Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.

Abstract: A method of implanting carbon ions into a target substrate, including: ionizing a carbon containing dopant material to produce a plasma having ions; optionally co-flowing an additional gas or series of gases with the carbon-containing dopant material; and implanting the ions into the target substrate. The carbon-containing dopant material is of the formula CwFxOyHz wherein if w=1, then x>0 and y and z can take any value, and wherein if w>1 then x or y is >0, and z can take any value. Such method significantly improves the efficiency of an ion implanter tool, in relation to the use of carbon source gases such as carbon monoxide or carbon dioxide.

Abstract: A method of forming a III-Nitride based device comprising: (a) depositing first layers by MOCVD on a substrate, wherein the first layers comprise device layers of III-Nitride material; and (b) depositing epitaxial second layers over the first layers by at least one of sputtering, plasma deposition, pulsed laser deposition, or liquid phase epitaxy, wherein the second layers comprise III-Nitride material and define at least partially a tunnel junction.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.

Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.

Abstract: A method of making a thin film transistor, the method including: providing an insulating layer on a semiconductor substrate, forming a semiconductor layer on the insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure comprises a nanowire; forming an opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, and the conductive film layer is divided into two regions by the nano-scaled channel, one region is used as a source electrode, and the other region is used as a drain electrode; forming a gate electrode on the semiconductor substrate.

Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region. The semiconductor device further includes a cell array disposed in the cell array region and including a plurality of cell strings connected to a bit line. The bit line extends in a first direction. The semiconductor device additionally includes a first cell row disposed in the peripheral circuit region and including a plurality of first cells arranged in a second direction crossing the first direction. The first and second directions being parallel to an upper surface of the substrate. The semiconductor device further includes a plurality of first interconnect lines each having a longitudinal axis in the first direction and connected to the plurality of first cells, and a plurality of first power lines extending in the second direction and connected to the plurality of first cells through the first interconnect lines.

Abstract: A method of making nano-scaled channel, the method including: locating a first photoresist layer, a nanowire structure, and a second photoresist layer on a surface of a substrate, and the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises an nanowire; forming an opening in the first photoresist layer and the second photoresist layer to expose a portion of the surface of the substrate to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening, and both ends of the nanowire are sandwiched between the first photoresist layer and the second photoresist layer; and depositing a thin film layer on the exposed surface of the substrate using the a nanowire as a mask, wherein the thin film layer defines a nano-scaled channel corresponding to the at least one nanowire.

Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.