Abstract: One example provides a microelectromechanical systems (MEMS) device that includes a number of silicon die over-molded with an overmold material, a number of active areas formed on the silicon die, the active areas including at least one sensor to sense a number of attributes of a fluid introduced to the at least one sensor, and a fan-out layer coupled to the silicon die, the fan-out layer including a number of fluid channels formed therein that interface with active areas of the silicon die and allow the fluid to flow to the at least one sensor.

Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.

Abstract: Along dicing lines, cutting grooves that reach a rear surface from a front surface are formed by a first dicing blade in a semiconductor wafer, completely separating the semiconductor wafer into individual semiconductor chips by the cutting grooves. Thereafter, by a second dicing blade that is constituted by abrasive grains having a mean grit size smaller than that of the first dicing blade and that has a blade width wider than that of the first dicing blade, side walls of the cutting grooves, i.e., side surfaces of the semiconductor chips are polished, approaching a specular state.

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate.

Abstract: A template for imprint lithography can include an active area that includes a plurality of tiers including a first tier and a second tier, and a first feature within the first tier or the second tier. In another embodiment, the first and second tiers include features, and the average feature depth or height within the first tier may be substantially the same as or different from the average feature depth or height within the second tier. The template can be used in imprinting a formable layer to form a patterned resist layer over a device substrate that has at least two tiers. The template and its use are well suited for device substrates having exposed surfaces at significantly different elevations, particularly where planarization would be complicated or nearly impossible to implement.

Abstract: A substrate has a first surface and a second surface facing each other. A photoelectric conversion region includes a plurality of photoelectric conversion devices provided in the substrate. An interlayered insulating layer is provided on the first surface of the substrate. A plurality of wires is provided on the interlayered insulating layer. An inter-wire insulating layer covers the plurality of wires. A plurality of micro lenses is provided on the second surface of the substrate. A grid pattern is provided in at least one of the interlayered insulating layer and the inter-wire insulating layer. The grid pattern, when viewed in a plan view, overlaps a region between two adjacent photoelectric conversion devices of the plurality of photoelectric conversion devices.

Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

Abstract: The present application provides an array substrate and a display device. The array substrate includes a substrate provided with a display region and a non-display region. The display region is configured to display. The non-display region includes a groove region. The groove region has a light transmittance greater than that of the display region. The display device includes the above-described array substrate.

Abstract: Various embodiments are directed to a light pipe. The light pipe may include a channel within a substrate of an image sensor. The channel may be formed by a plurality of layers. The plurality of layers may include a first layer and a second layer. The second layer may be spaced apart from the first layer along an axis of the channel.

Abstract: A display substrate includes a first switching element electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction, an organic layer disposed on the first switching element, a shielding electrode disposed on the organic layer and overlapping the data line, a pixel electrode disposed on the same layer as the shielding electrode and a light-blocking pattern disposed on the shielding electrode and adjacent to a corner of the pixel electrode

Abstract: According to the disclosure, a method for producing an organic component is provided. The method includes providing a carrier substrate; forming an electrically conductive layer on or above the carrier substrate; applying an electrical potential to the electrically conductive layer; and forming at least one organic, functional layer for forming the organic component on or above the electrically conductive layer at least partly during the process of applying the electrical potential to the electrically conductive layer.

Abstract: A display device according to an embodiment of the present invention includes: a first substrate; light emitting elements arranged on the first substrate and including electrodes; a first insulation layer covering an edge of each of the electrodes on the first substrate; a second insulating section arranged on the light emitting elements and overlapping with the light emitting elements in plan view; a third insulating section arranged the banks, overlapping with the banks in plan view and having a lower refractive index than a refractive index of the second insulating section.

Abstract: The disclosure provides methods and compositions therefor for treating a surface wherein a surface treatment layer is formed on the surface, thereby minimizing or preventing pattern collapse as the surface is subjected to typical cleaning steps in the semiconductor manufacturing process.

Abstract: A printed electronic device may comprise a plurality of contact pads arranged in a pattern, a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads, and a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.

Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.