Patents Examined by Caridad Everhart
  • Semiconductor device and method
    Patent number: 10847637
    Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Cryogenic oxidation of metal layer of magnetic-tunnel-junction (MTJ) device
    Patent number: 10847713
    Abstract: A method is for manufacturing a magnetic-tunnel-junction (MTJ) device. The method includes forming a free magnetic layer over a substrate, forming a metal layer over the free magnetic layer, and oxidizing the metal layer by exposing the metal layer to an oxidation gas at a temperature of 250° K or less.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whan Kyun Kim, Eun Sun Noh, Joon Myoung Lee, Woo Chang Lim, Jun Ho Jeong
  • Low-k gate spacer and methods for forming the same
    Patent number: 10833170
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Semiconductor devices including transistors comprising a charge trapping material, and related systems and methods
    Patent number: 10833087
    Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fredrick D. Fishburn, Haitao Liu, Soichi Sugiura, Oscar O. Enomoto, Mark A. Zaleski, Keisuke Hirofuji, Makoto Morino, Ichiro Abe, Yoshiyuki Nanjo, Atsuko Otsuka
  • Capacitive tuning circuit using RF switches with PCM capacitors and PCM contact capacitors
    Patent number: 10833004
    Abstract: A capacitive tuning circuit includes radio frequency (RF) switches connected to an RF line. Each RF switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, and RF terminals having lower metal portions and upper metal portions. Alternatively, the RF terminals can have a trench metal liner separated from a trench metal plug by a dielectric liner. At least one capacitor is formed in part by at least one of the lower metal portions, upper metal portions, or trench metal liner. The capacitive tuning circuit can be set to a desired capacitance value when a first group of the RF switches is in an OFF state and a second group of the RF switches is in an ON state.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: November 10, 2020
    Assignee: Newport Fab, LLC dba Jazz Semiconductor
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Display panel and manufacturing method thereof, display device
    Patent number: 10825842
    Abstract: The present disclosure provides a display panel, a manufacturing method of a display panel, and a display device including the display panel. The display panel includes: an array substrate, including a display region, a non-display region around the display region, and data lines extending into the non-display region; a planarization layer, covering the data lines; and a metal wiring layer, disposed on the planarization layer in the non-display region, and including a plurality of metal wirings spaced apart from each other and corresponding to the data lines.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 3, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Zhen Wang, Jian Sun, Han Zhang
  • Organic light emitting diode lighting apparatus and method of fabricating the same
    Patent number: 10826024
    Abstract: An organic light emitting diode lighting apparatus can include a substrate having an emitting area and first and second non-emitting areas; an auxiliary electrode in the first non-emitting area on the substrate; an overcoating layer in the emitting area on the substrate, the overcoating layer having a microlens including a plurality of convex portions and a plurality of concave portions; a first electrode on the auxiliary electrode and the overcoating layer, the first electrode including at least one open portion exposing the overcoating layer in the second non-emitting area; a gas blocking pattern covering the at least one open portion; and a light emitting layer and a second electrode disposed on the first electrode and the gas blocking pattern.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 3, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kang-Ju Lee, Tae-Shick Kim
  • Semiconductor device and method for manufacturing the same
    Patent number: 10818784
    Abstract: A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 27, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Self-aligned double patterning process and semiconductor structure formed using thereof
    Patent number: 10818505
    Abstract: A method comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island and a first mandrel strip, the mandrel island comprises a first sidewall and a second sidewall perpendicular to the first sidewall, and the first mandrel strip extends from the first sidewall of the mandrel island. A first spacer is formed along the first and second sidewalls of the mandrel island and a sidewall of the first mandrel strip. The first mandrel is removed from the target layer. The target layer is patterned when the first spacer remains over the target layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Wang, Kuo-Chyuan Tzeng
  • Stacked image sensor having a barrier layer
    Patent number: 10818720
    Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Shu-Ting Tsai, Cheng-Ying Ho, Tzu-Hsuan Hsu, Shih-Pei Chou
  • Integration and bonding of micro-devices into system substrate
    Patent number: 10818622
    Abstract: This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 27, 2020
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Bahareh Sadeghimakki
  • Method of preparing graphene quantum dot, hardmask composition including the graphene quantum dot obtained by the method, method of forming patterns using the hardmask composition, and hardmask formed from the hardmask composition
    Patent number: 10808142
    Abstract: Provided are a method of preparing a graphene quantum dot, a graphene quantum dot prepared using the method, a hardmask composition including the graphene quantum dot, a method of forming a pattern using the hardmask composition, and a hardmask obtained from the hardmask composition. The method of preparing a graphene quantum dot includes reacting a graphene quantum dot composition and an including a polyaromatic hydrocarbon compound and an organic solvent at an atmospheric pressure and a temperature of about 250° C. The polyaromatic hydrocarbon compound may include at least four aromatic rings.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwon Kim, Minsu Seol, Hyeonjin Shin, Dongwook Lee, Yunseong Lee, Seongjun Jeong, Alum Jung
  • Organic-inorganic hybrid material and method for silicon surface passivation
    Patent number: 10811558
    Abstract: A relevant technological challenge is the low cost and abundant materials development for silicon surface passivation for applications in optoelectronic devices, in particular in solar cells by scalable industrial methods. In the present invention, a new hybrid material comprising PEDOT:PSS and transparent conducting oxide nanostructures is developed and a method is proposed to fabricate the composite material that passivates well the silicon surface to be used by means of a thin composite film of thickness below 200 nm.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 20, 2020
    Assignees: INSTITUTT FOR ENERGITEKNIKK, UNIVERSIDAD COMPLUTENSE DE MADRID
    Inventors: Ana Cremades Rodriguez, Chang Chuan You, David Maestre Varea, Erik Stensrud Marstein, Geraldo Cristian Vasquez Villanueva, Halvard Haug, Javier Piqueres De Noriega, Jose Maria Gonzalez Calbet, Julio Ramirez Castellanos, Maria Taeno Gonzalez, Miguel Garcia Tecedor, Smagul Karazhanov
  • Microelectronic device utilizing stacked vertical devices
    Patent number: 10804266
    Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Multivalent oxide cap for analog switching resistive memory
    Patent number: 10797235
    Abstract: A memory includes a base oxide provided between a first electrode and a second electrode, and a multivalent oxide provided between the first electrode and the second electrode. The multivalent oxide switches between at least two oxidative states.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Method for forming epitaxial layer at low temperature
    Patent number: 10796915
    Abstract: Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700° C.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 6, 2020
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Doo Yeol Ryu, Seung Woo Shin, Cha Young Yoo, Woo Duck Jung, Ho Min Choi, Wan Suk Oh, Hui Sik Kim, Eun Ho Kim, Seong Jin Park
  • Tapered VA structure for increased alignment tolerance and reduced sputter redeposition in MTJ devices
    Patent number: 10790001
    Abstract: A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Nathan Philip Marchack
  • Molecular coatings of nitride semiconductors for optoelectronics, electronics, and solar energy harvesting
    Patent number: 10784410
    Abstract: Gallium nitride based semiconductors are provided having one or more passivated surfaces. The surfaces can have a plurality of thiol compounds attached thereto for enhancement of optoelectronic properties and/or solar water splitting properties. The surfaces can also include wherein the surface has been treated with chemical solution for native oxide removal and/or wherein the surface has attached thereto a plurality of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof to create a treated surface for enhancement of optoelectronic properties and/or solar water splitting properties. Methods of making the gallium nitride based semiconductors are also provided.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 22, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Tien Khee Ng, Chao Zhao, Davide Priante, Boon S. Ooi, Mohamed Ebaid Abdrabou Hussein
  • Light emitting device reflective bank structure
    Patent number: 10784236
    Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 22, 2020
    Assignee: Apple Inc.
    Inventors: Kapil V. Sakariya, Andreas Bibl, Hsin-Hua Hu
  • Integrated semiconductor device and method for manufacturing the same
    Patent number: 10777551
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son