Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.

Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

Abstract: A method for contacting a metallic contact pad embedded in a printed circuit board layer sequence, comprising the steps of producing a first hole matrix having a plurality of holes in a surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, of applying a metal layer in order to at least partly fill the holes of the first hole matrix, of producing a second hole matrix having a plurality of holes in the surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, wherein the holes of the second hole matrix are arranged in a manner offset relative to the holes of the first hole matrix, and of applying a metal layer in order to at least partly fill the holes of the second hole matrix, and a correspondingly produced printed circuit board.

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: There is provided a nitride semiconductor substrate, including: a substrate configured as an n-type semiconductor substrate; and a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons, wherein a concentration of the donors in the drift layer is 5.0×1016/cm3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and a difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually increased from a substrate side toward a surface side of the drift layer.

Abstract: A display device includes a display panel having a first region, a second region spaced apart from the first region, and a bending region between the first region and the second region, the bending region being bent along a bending axis, a protective film including a first part on a first surface of the first region of the display panel, the first part having an opening at a center thereof that exposes the first surface of the display panel, and a second part on a first surface of the second region of the display panel, and a functional layer on the first surface of the display panel exposed by the opening.

Abstract: An OLED device comprising a substrate with a top surface; a first electrode covering the top surface of the substrate; a first insulating structure patterned over a portion of the first electrode where the pattern defines an inside area of the first electrode that is completely surrounded by the insulating structure, and an outside area of the first electrode not covered by the insulating structure; at least one organic layer for light emission within the inside area defined by the insulating structure; a second electrode over the at least one organic layer within the inside area defined by the insulating structure and at least partially over the first insulating structure; a cover slip located at least over the second electrode in the inside area defined by the insulating structure; and an electrically conductive solder seal making a hermetic seal between the insulating structure and the cover slip where the solder seal is in electrical contact with the second electrode.

Abstract: A packaged device, having a package, including a first dissipative region, a second dissipative region, a first connection element and a second connection element. A die of semiconductor material is arranged within the package, carried by the first dissipative region. The first and second dissipative regions extend at a distance from each other, and the first and second connection elements extend at a distance from each other between the first and second dissipative regions. The first dissipative region, the second dissipative region, the first connection element, and the second connection element are hollow and form a circuit containing a cooling liquid.

Abstract: A light-emitting device comprises a first light-emitting semiconductor stack comprising a first active layer; a second light-emitting semiconductor stack below the first light-emitting semiconductor stack, wherein the second light-emitting semiconductor stack comprises a second active layer; a reflector between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack; a protecting layer between the reflector and the second light-emitting semiconductor stack; and wherein the first light-emitting semiconductor stack further comprises a first semiconductor layer and a second semiconductor layer sandwiching the first active layer, the second light-emitting semiconductor stack further comprises a third semiconductor layer and a fourth semiconductor layer sandwiching the second active layer, wherein the second semiconductor layer has a first band gap, the third semiconductor layer has a second band gap, and the protecting layer has a third band gap between the first band gap an

Abstract: Provided is an electrode structure having a transparent electrode, a light blocking pattern provided on the transparent electrode, an auxiliary electrode pattern provided on the light blocking pattern, and an organic insulating pattern covering the light blocking pattern and the auxiliary electrode pattern, wherein a line width of the light blocking pattern is larger than a line width of the auxiliary electrode pattern. Also provided are an electronic device including the electrode structure, and a method of manufacturing the electrode structure.

Abstract: The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor substrate, a first pillar and a second pillar over the semiconductor substrate, an isolation layer over the semiconductor substrate, and a first contact pad and a second contact pad embedded in the isolation layer. A first upper surface of the first pillar is higher than a second upper surface of the second pillar. The first pillar and the second pillar are laterally surrounded by the isolation layer. The first contact pad is disposed over the first pillar. The second contact pad is disposed over the second pillar, and a first pad width of the first contact pad is not greater than a second pad width of the second contact pad.

Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.

Abstract: A flexible display device includes a flexible display panel having a bending area to be folded, and including a display substrate, and a thin-film encapsulation layer above the display substrate, a driving portion, and a function layer below the flexible display panel, and including a step portion below which the flexible display panel is electrically connected to the driving portion.

Abstract: Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes may include a photon-reflective material.

Abstract: A method for manufacturing a semiconductor structure with reduced bowing for applications in the field of power electronics, photonics, optoelectronics, solar energy conversion and the like, which comprises: a step of providing at least a first layer of a first semiconductor material, said first layer comprising a substrate of said first semiconductor material, which extends along a first reference plane, and a plurality of first portions of said first semiconductor material, which are mutually spaced and extend in elevation from said substrate along axes perpendicular to said first reference plane, said first portions having ends in distal position with respect to said substrate; a step of providing at least a second layer of a second semiconductor material, said second layer comprising second portions of said second semiconductor material, each of which is joined to the ends of a plurality of said first portions, said second portions being mutually spaced and extending along a second reference plane paralle

Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

Abstract: A method of and system for adhesive bonding by a) providing a polymerizable adhesive composition on a surface of an element to be bonded to form an assembly; b) irradiating the assembly with radiation at a first wavelength capable of vulcanization of bonds in the polymerizable adhesive composition by activation of sulfur-containing compound with at least one selected from x-ray, e-beam, visible, or infrared light to thereby generate ultraviolet light in the polymerizable adhesive composition; and c) adhesively joining two or more components together by way of the polymerizable adhesive composition.

Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.