Patents Examined by Caridad M. Everhart
  • Patent number: 8669550
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: March 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8288199
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8216949
    Abstract: A method lor integrated circuit fabrication is disclosed. A spacer pattern is provided including a plurality ot spacers in an array region of a partially-fabricated integrated circuit. Each spacer is at least partly defined by opposing open volumes extending along lengths of the spacers. A pattern is subsequently defined in a periphery region of the partially-fabricated integrated circuit. A consolidated pattern is formed by concurrently transferring the spacer pattern and the pattern in the periphery region into an underlying masking layer. The consolidated pattern is transferred to an underlying substrate.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: July 10, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Mirzafer K Abatchev, Gurtej Sandhu, Luan Tran, William T Rericha, D. Mark Durcan
  • Patent number: 8163586
    Abstract: A method for producing a device with at least one suspended membrane, including the following steps: Producing a trench through a first sacrificial layer and a second layer deposited on the first sacrificial layer, the trench completely surrounding at least a portion of the first sacrificial layer and at least a portion of the second layer, filling all or a portion of the trench with at least one material capable of resisting at least one etching agent, and etching the portion of the first sacrificial layer with the etching agent through at least one opening made in the second layer, the portion of the second layer forming at least one portion of the suspended membrane.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: April 24, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Patrice Rey, Mouna Salhi
  • Patent number: 8071440
    Abstract: A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: December 6, 2011
    Assignee: United Microelectronics Corporation
    Inventors: Po-Sheng Lee, Yu-Hsien Lin, Wen-Fang Lee
  • Patent number: 8003483
    Abstract: Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor la
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: August 23, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Akihisa Shimomura, Junpei Momo, Motomu Kurata, Taiga Muraoka, Kosei Nei
  • Patent number: 7998840
    Abstract: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having a device area and a peripheral excess area surrounding the device area, the surface of the device area being higher than the surface of the peripheral excess area, involving a first step for forming a deteriorated layer in the insides of the peripheral excess area and device area by applying a laser beam to the peripheral excess area and the device area with its focal point set in the material of the peripheral excess area and the device area from the front surface side of the wafer; and a second step for forming a deteriorated layer in the inside of the device area by applying a laser beam to the device area with its focal point set in the material of the device area without applying the laser beam to the peripheral excess area.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: August 16, 2011
    Assignee: Disco Corporation
    Inventor: Yosuke Watanabe
  • Patent number: 7998790
    Abstract: A method of manufacture of an integrated circuit die packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 16, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 7993972
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 9, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao
  • Patent number: 7981787
    Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: July 19, 2011
    Assignee: OKI Semiconductor Co., Ltd.
    Inventors: Takayuki Izumi, Ryoji Shigemasa, Tomoyuki Ohshima
  • Patent number: 7977211
    Abstract: The current invention presents a method for thinning wafers. The method uses a two-step process, whereby first the carrier wafer (2) is thinned and in a second step the device wafer (1) is thinned. The method is based on imprinting the combined thickness non-uniformities of carrier (2) and glue layer (3) essentially on the carrier (2), with a resulting low TTV of the wafer (100) after thinning.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 12, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventor: Ricardo Cotrin Teixeira
  • Patent number: 7964424
    Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: June 21, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
  • Patent number: 7964465
    Abstract: A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Andres Bryant, Edward Joseph Nowak
  • Patent number: 7951711
    Abstract: Methods and compositions for depositing metal films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising gold, silver, or copper. More specifically, the disclosed precursor compounds utilize pentadienyl ligands coupled to a metal to increase thermal stability. Furthermore, methods of depositing copper, gold, or silver are disclosed in conjunction with use of other precursors to deposit metal films. The methods and compositions may be used in a variety of deposition processes.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: May 31, 2011
    Assignee: L'Air Liquide Societe Anonyme pour l'Etude Et l'Exploitation des Procedes Georges Claude
    Inventor: Christian Dussarrat
  • Patent number: 7943479
    Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Angelo Pinto, Manuel A. Quevedo-Lopez
  • Patent number: 7943439
    Abstract: A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: May 17, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 7939395
    Abstract: Structures and methods for integrating a thick oxide high-voltage metal-oxide-semiconductor (MOS) device into a thin oxide silicon-on-insulator (SOI). A method of forming a semiconductor structure includes forming first source and drain regions of a first device below a buried oxide layer of a silicon-on-insulator (SOI) wafer, forming a gate of the first device in a layer of semiconductor material above the buried oxide layer; and forming second source and drain regions of a second device in the layer of semiconductor material above the buried oxide layer.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lillian Kamal, legal representative, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Yun Shi, William R. Tonti
  • Patent number: 7939388
    Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Hisao Nagai, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7939424
    Abstract: A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: May 10, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Yuri Erokhin, Paul Sullivan, Steven R. Walther, Peter Nunan
  • Patent number: 7939393
    Abstract: Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: May 10, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Weize Xiong, Cloves Rinn Cleavelin