Abstract: A method of forming an organic thin film transistor comprising source and drain electrodes with a channel region therebetween, a gate electrode, a dielectric layer disposed between the source and drain electrodes and the gate electrode, and an organic semiconductor disposed in at least the channel region between the source and drain electrodes, said method comprising: seeding a surface in the channel region with crystallization sites prior to deposition of the organic semiconductor; and depositing the organic semiconductor onto the seeded surface whereby the organic semiconductor crystallizes at the crystallization sites forming crystalline domains in the channel region.

Abstract: Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like the ingot, and to transfer this structure into a respective silicon process step. Some embodiments provide a process that allows one to structure any complex structured layer stacks, where the layers can be applied on top of each other using, e.g., bonding technology.

Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.

Abstract: A manufacturing method of a light emitting diode (LED) apparatus includes the steps of: forming at least one temporary substrate, which is made by a curable material, on a LED device; and forming at least a thermal-conductive substrate on the LED device. The manufacturing method does not need the step of adhering the semiconductor structure onto another substrate by using an adhering layer, and can make the devices to be in sequence separated after removing the temporary substrate, thereby obtaining several LED apparatuses. As a result, the problem of current leakage due to the cutting procedure can be prevented so as to reduce the production cost and increase the production yield.

Abstract: A method for manufacturing a solid-state image capturing apparatus including a pixel array constituted of a plurality of pixels, is provided, where each of the plurality of pixels includes a photoelectric conversion section, the method comprising the steps of: forming an impurity diffusion area in a surface area of a semiconductor substrate; and forming a plurality of different impurity diffusion areas in the surface area of the semiconductor substrate, other than the impurity diffusion area constituting the photoelectric conversion section.

Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.

Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

Abstract: After forming a first gate electrode and a second gate electrode on a semiconductor substrate, a silicon oxide film is formed to cover an n-channel MISFET forming region, and a p-channel MISFET forming region is exposed. Subsequently, after a first element supply film made of, for example, an aluminum oxide film is formed on the whole surface of the semiconductor substrate, a heat treatment is performed. By this means, a high-concentration HfAlO film and a low-concentration HfAlO film are formed by diffusing aluminum into the first insulating film just below the second gate electrode. Thereafter, by using a magnesium oxide film as a second element supply film, magnesium is diffused into the first insulating film just below the first gate electrode, thereby forming a high-concentration HfMgO film and a low-concentration HfMgO film.

Abstract: A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars.

Abstract: A substrate treating device comprising a treatment chamber for storing and treating substrates and a heating device having a heating element and a heat insulator and heating the substrates in the treatment chamber by the heating element. The heating element is so formed that only its one end is held by a holding part, and a projection projected to the treatment chamber side at the intermediate part of the heating element and positioned in proximity to or in contact with the heating element is formed on the heat insulator. A pin with an enlarged part is passed through the heating element and the heat insulator at the intermediate part of the heating element and the enlarged part is positioned in proximity to or in contact with the heating element. The plurality of projections may be formed on the heat insulator and the pins may be disposed between these plurality of projections.

Abstract: The present invention provides an integrated circuit package system comprising: attaching a die platform to an integrated circuit die; mounting the integrated circuit die over an external interconnect with a bottom side of the external interconnect partially within the die platform; connecting the integrated circuit die and the external interconnect; and forming an encapsulation over the integrated circuit die with the external interconnect partially exposed.

Abstract: A method for producing a sensor array including a monolithically integrated circuit is described as well as a sensor array. This sensor array has a micromechanical sensor structure, in which a first partial structure which is associated with the sensor structure is produced at the same time as a second partial structure which is associated with the circuit, a process variation of the first partial structure being performed in order to adjust a structure property of the sensor structure while the second partial structure remains the same.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.

Abstract: The present invention provides a method of manufacturing a bonded wafer. The method includes forming an oxygen ion implantation layer in an active layer wafer having a substrate resistivity of 1 to 100 m?cm by implanting oxygen ions in the active layer wafer, bonding a base wafer and the active layer wafer directly or through an insulating layer to form a bonded wafer, heat treating the bonded wafer to strengthen the bond and convert the oxygen ion implantation layer into a stop layer, grinding, polishing, and/or etching, from the active layer wafer surface side, the bonded wafer in which the bond has been strengthened to expose the stop layer on a surface of the bonded wafer, removing the stop layer, and subjecting the bonded wafer from which the stop layer has been removed to a heat treatment under a reducing atmosphere to diffuse an electrically conductive component comprised in the active layer wafer.

Abstract: Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.

Abstract: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress.

Abstract: An organic thin film transistor array panel is provided, which includes: a substrate; a data line formed on the substrate and including a source electrode; a drain electrode formed on the substrate and separated from the data line; an organic semiconductor disposed on the source electrode and the drain electrode; a gate insulator formed on the organic semiconductor; a gate line including a gate electrode disposed on the gate insulator; a passivation layer formed on the gate line and having a first contact hole on the drain electrode; a pixel electrode connected to the drain electrode through the first contact hole; and an opaque light blocking member disposed under the organic semiconductor.

Abstract: The invention relates to a semiconductive device comprising a die with at least one defined hot-spot area lying in a plane on the die and a cooling structure comprising nanotubes such as carbon nanotubes extending in a plane different than the plane of the hot-spot area and outwardly from the plane of the hot-spot area. The nanotubes are operatively associated with the hot-spot area to decrease any temperature gradient between the hot-spot area and at least one other area on the die defined by a temperature lower than the hot-spot area. A matrix material comprising a second heat conducting material substantially surrounds the nanotubes and is operatively associated with and in heat conducting relation with the other area on the die defined by a temperature lower than the hot-spot area.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.