Patents Examined by Cassandra F Cox
  • Patent number: 10812065
    Abstract: There is provided a power supply control apparatus for connection to electrical inputs of an electronic device wherein each electrical input is operatively connected to a power source having a sequencer circuit and a control element, the sequencer circuit including sequencer stage(s). The sequencer circuit selectively receives an indication signal, the sequencer circuit selectively receives a positive indication signal indicative of a voltage supplied to a first of the electrical inputs reaching or passing a predefined voltage threshold, and the sequencer circuit selectively provides a control signal to the control element, the control element triggerable by a positive control signal. Each sequencer stage includes circuit elements, the first selectively receives an input signal and selectively provides an intermediate signal to the second, the second selectively provides an output signal.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: October 20, 2020
    Assignee: GENERAL ELECTRIC TECHNOLOGY GMBH
    Inventor: Jun Yan
  • Patent number: 10811963
    Abstract: A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Xiaoqun Liu, Madan Mohan Reddy Vemula
  • Patent number: 10804904
    Abstract: A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits. Each serializer circuit generates a sampled sync loss signal by sampling the sync loss pulse in accordance with a parallel clock signal, and a Boolean value is assigned to the sampled sync loss signal and output. A logic block detects a sync loss when the sampled sync loss signal of any serializer circuit is out of sync from the sync loss pulse based on the Boolean value.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tamal Das, Nageswara Rao Kunchapu, Umamaheswara Reddy Katta
  • Patent number: 10790794
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage interface and provide a redriver connected between a pair of input pads and a pair of output pads. The interface may further provide a signal detection circuit connected to the pair of input pads and configured to bias a pair of input termination resistors connected to the input pads with one of a supply voltage and a regulator voltage. The signal detection circuit may be further configured to enable/disable the redriver for a period of time.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 29, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Athar Ali Khan. P
  • Patent number: 10788870
    Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Gaetano Di Stefano, Mirko Dondini
  • Patent number: 10784860
    Abstract: A gate driver includes a first transistor and a second transistor connected in series between a first and a second power supply line, connection nodes thereof are output nodes of the gate driver, the first and second transistors being configured to operate in a complementary manner, a power supply circuit for applying an offset voltage to a source of the transistor, and a switching circuit for performing switching control to apply the offset voltage output from the power supply circuit to the source of the transistor or to apply the second potential to the source of the transistor. The switching circuit is configured to switch so as to apply the offset voltage to the source of the transistor in accordance with a timing of turning off the gate of the transistor and to apply the second potential to the source in accordance with a timing of turning on the gate.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: September 22, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinji Sakai
  • Patent number: 10784765
    Abstract: A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die. Multi-output POL circuits may be used in conjunction with on-chip rail-selection and regulation circuitry to further improve efficiency.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 22, 2020
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Andrew T. D'Amico
  • Patent number: 10778148
    Abstract: A power detector with a main transconductance stage and a Gilbert switch stage coupled to one another. Current sources are coupled between the main transconductance and the Gilbert switch stages. Each of the current sources is configured to generate a cascoded PMOS trickle current under the control of a DAC to control the effective voltage of the Gilbert switch stage. This mitigates the DC offsets resulting in enhanced sensitivity of the Gilbert switch stage. An increase in the conversion gain of a system using a Gilbert switch stage, for a given LO swing, is therefore obtained for a very small increase in DC power.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: September 15, 2020
    Assignee: Raytheon Company
    Inventors: Wais Ali, Ronald Tirado, Bryan Fast
  • Patent number: 10778164
    Abstract: An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 15, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Wei Liang
  • Patent number: 10771049
    Abstract: The present document describes a control circuit and a method for controlling a power transistor, wherein the power transistor has a drain, a gate and a source. The power transistor has a body diode. The control circuit is configured to predict a time instant at which a drain potential at the drain falls below a source potential at the source of the power transistor by more than a diode threshold voltage of the body diode. Furthermore, the control circuit is configured to apply a pre-bias potential and/or provide a pre-bias current to the gate of the power transistor in dependence the predicted time instant, such that a conducting channel between the drain and the source is provided, which at least partially takes over current which would otherwise flow through the body diode.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 8, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ambreesh Bhattad, Horst Knoedgen
  • Patent number: 10763873
    Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2? radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 1, 2020
    Assignee: Eridan Communications, Inc.
    Inventor: Richard W. D. Booth
  • Patent number: 10755734
    Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 25, 2020
    Assignee: Seagate Technology LLC
    Inventors: Jason Bellorado, Marcus Marrow, Zheng Wu
  • Patent number: 10756716
    Abstract: An electronic device according to the present disclosure is an electronic device having a function of removing glitches contained in a signal, and includes a glitch removal circuit which removes glitches from an inputted signal, and a count unit which counts a number of times removing glitches.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 25, 2020
    Assignee: FANUC CORPORATION
    Inventor: Takaaki Komatsu
  • Patent number: 10747250
    Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-won Lee, Nam-seog Kim
  • Patent number: 10749509
    Abstract: A capacitive-coupled level shifter includes: an input having a positive input terminal and a negative input terminal, the input configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive divider circuit comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal of the comparator circuit. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of the modulated signal. A level shifter system which includes the capacitive-coupled level shifter is also described.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Giacomo Cascio, Salvatore Angelo Della Fortuna
  • Patent number: 10745023
    Abstract: A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 18, 2020
    Assignee: INTEL CORPORATION
    Inventors: Amit Kumar Srivastava, Asad Azam, Jagannadha Rapeta
  • Patent number: 10742219
    Abstract: A frequency divider includes a circuit that receives an input clock signal having a period T on an input port thereof and generates an output clock signal on an output port thereof having a period MT in response to a control signal specifying M is disclosed. Here, M is a positive integer and all transitions between logical one and logical zero in the output clock signal occur at integer multiples of T. In one embodiment, the circuit includes a module string having characterized by N identical modules connected in series to form a string of modules. Each module is configured such that when the clock signal having period T is input to the first module, the output clock signal having a period of MT is output from the last module, where M can have any value between one and a maximum number that depends on N.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 11, 2020
    Assignee: BAE Systems Imaging Solutions Inc.
    Inventors: Khai Nguyen, Andrew C. Ng
  • Patent number: 10739807
    Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Guenole Lallement, Fady Abouzeid
  • Patent number: 10734972
    Abstract: A switch-type phase shifter including a phase shifting unit is provided. The phase shifting unit includes two half circuits and a first switch connected to the half circuits and receiving a first control signal. Each half circuit includes a first variable capacitor, a second variable capacitor, a second switch and a variable inductor. The two ends of the first variable capacitor are coupled to the input and the control nodes of the half circuit respectively. The two ends of the second variable capacitor are coupled to the output and control nodes of the half circuit respectively. The first and second ends of the second switch are coupled to the output and input nodes respectively, and the third end thereof is coupled to the control node and receives a second control signal. The two ends of the variable inductor are coupled to the input and output nodes respectively.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 4, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Heng Lin, Fang-Yao Kuo, Zuo-Min Tsai
  • Patent number: 10734893
    Abstract: A power converter includes a charge pump in which transistors transition between conducting and non-conducting states thereby causing said pump capacitors to be interconnected in different arrangements at different times. Among the transistors is one that transitions into a conducting state when a source and gate of that transistor are at equal potentials.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: August 4, 2020
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Arezu Bagheri