Patents Examined by Cassandra F Cox
  • Patent number: 12381544
    Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: August 5, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei Shuo Lin
  • Patent number: 12376379
    Abstract: An array substrate includes a base substrate including a first surface and a second surface, scanning signal lines disposed on the first surface, at least two groups of shift register circuits disposed in a display area of the first surface, and at least one fan-out structure disposed on the second surface. Each scanning signal line extends along a first direction. Each group of shift register circuits includes a plurality of shift register circuits along a second direction. Each shift register circuit is coupled to a scanning signal line. The fan-out structure is coupled to the shift register circuits. At least one group of shift register circuits is disposed in a non-edge region of the display area. The shift register circuit disposed in the non-edge region is configured to transmit a scanning signal to the scanning signal line at both sides of the shift register circuit along the first direction.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: July 29, 2025
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dongni Liu, Minghua Xuan, Feng Qu, Qi Qi
  • Patent number: 12368439
    Abstract: A method includes receiving electromagnetic signals containing pulses. The method also includes converting the pulses contained in the electromagnetic signals into an electrical signal that identifies at least some of leading or trailing edges of the pulses. The method further includes repeatedly (i) accumulating the electrical signal to generate a voltage using an integrating circuit and (ii) resetting the integrating circuit in response to the voltage of the integrating circuit meeting or exceeding a threshold voltage. In addition, the method includes providing a count value identifying a number of times that the voltage of the integrating circuit meets or exceeds the threshold voltage. Each time the voltage of the integrating circuit meets or exceeds the threshold voltage is representative of a specific number of pulses received in the electromagnetic signals.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: July 22, 2025
    Assignee: Raytheon Company
    Inventors: James J. Richardson, David D. Crouch, Spencer A. Miller, Taylor B. Boultinghouse
  • Patent number: 12368443
    Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: July 22, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinwook Lee, Joohwan Kim, Junyoung Park, Jindo Byun, Eunseok Shin, Junghwan Choi
  • Patent number: 12368440
    Abstract: Systems and methods relate a device for monitoring or tracking clock frequency. The device can include a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal, and a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal is indicative of a second number of cycles of the sample clock signal occurring during the first number of cycles of the reference clock signal. The device can also include a third circuit configured to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal using the second signal.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: July 22, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Renfei Liu
  • Patent number: 12348230
    Abstract: An all-digital duty cycle corrector and a method for correcting a duty cycle of an output clock are provided. The all-digital duty cycle corrector includes a duty cycle adjustment circuit, an asynchronous sampler, a counter and a correction control circuit. The duty cycle adjustment circuit performs duty cycle adjustment on an input clock to generate the output clock according to a digital control code. The asynchronous sampler performs asynchronous sampling on the output clock to generate N sampling results at N time points, respectively. The counter counts a number of first logic values among the N sampling results to generate a counting result. The correction control circuit compares the counting result with a reference value to generate a comparison result, and selectively adjusts the digital control code according to the comparison result, in order to correct the duty cycle of the output clock.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: July 1, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventor: Tse-Hung Chen
  • Patent number: 12341503
    Abstract: Provided is a semiconductor device that is easily controlled. The semiconductor device includes a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential, wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: June 24, 2025
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masanori Tsukuda, Shinya Soneda, Koichi Nishi
  • Patent number: 12334934
    Abstract: A delay adjustment circuit according to an embodiment includes: a plurality of delay adjustment units connected in series, each of the plurality of delay adjustment units including one or more first delay elements (102) connected in series that delay an input signal on the basis of a clock, and a first selector (120) that outputs one of the input signal and an output of the first delay element at a last stage among the one or more first delay elements; and an output unit (103, 104, 130a, 130b, 140) that outputs a clock according to an output of the first selector included in a delay adjustment unit at a last stage among the plurality of delay adjustment units, in which each of the plurality of delay adjustment units includes a different number of the first delay elements.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: June 17, 2025
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Mitsushi Tabata, Takashi Masuda, Daisuke Suzuki
  • Patent number: 12334931
    Abstract: A signal conversion device for converting a single-ended input voltage into a differential input voltage having a positive input voltage and a negative input voltage is provided. During a sampling phase, a holding phase, and a common-mode voltage generation phase, a capacitor related to the positive input voltage is electrically connected to the single-ended input voltage, and a capacitor related to the negative input voltage is electrically connected to a preset voltage. During a single-ended to differential phase, the capacitor related to the positive input voltage is electrically connected to the preset voltage, and the capacitor related to the negative input voltage is electrically connected to the single-ended input voltage. Hence, the common-mode voltage is not related to a capacitance ratio, and the capacitors does not need to be designed as switching capacitors with multiple switches. No complex control is required, and the parasitic effect of the circuit can be reduced.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: June 17, 2025
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Yeh-Tai Hung, Ching-Yen Chiu, Chung Ming Hsieh
  • Patent number: 12334933
    Abstract: A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: June 17, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Seok Nam, Jin Gyu Kang, Jeong Woon Kong, Yong Seong Roh
  • Patent number: 12334935
    Abstract: A clock data recovery circuit of a display suitable for recovering a clock from a clock data signal. The clock data recovery circuit includes a clock recovery circuit configured to delay an input clock through delay units of multiple stages, and output delayed clocks from the delay units, respectively; and a data recovery circuit configured to recover data of a clock data signal using a recovered clock selected among the delayed clocks.
    Type: Grant
    Filed: May 20, 2024
    Date of Patent: June 17, 2025
    Assignee: LX SEMICON CO., LTD.
    Inventors: Jong Suk Lee, Seok Jae Oh, Won Kim
  • Patent number: 12334936
    Abstract: A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.
    Type: Grant
    Filed: July 1, 2024
    Date of Patent: June 17, 2025
    Assignee: RAMSCHIP, INC.
    Inventors: Deoksoo Kim, Jaegan Ko, Bongjoon Lee
  • Patent number: 12316328
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a data strobe generation circuit with a first via configuration and/or a data buffer circuit with a second configuration.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 27, 2025
    Assignee: Altera Corporation
    Inventors: Chooi Pei Lim, Eah Loon Alan Chuah, Eng Huat Lee, Marian Serban, Marian Cretu
  • Patent number: 12316306
    Abstract: According to one embodiment, a high frequency semiconductor integrated circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, first to fourth switch circuits. In a case where a coupling destination of the first input terminal is switched from the first output terminal to the second output terminal, a third switching operation changing the third switch circuit from an ON state to an OFF state and a fourth switching operation changing the fourth switch circuit from the OFF state to the ON state are finished, after a first switching operation changing the first switch circuit from the ON state to the OFF state and a second switching operation changing the second switch circuit from the OFF state to the ON state are finished.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: May 27, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Takayuki Teraguchi
  • Patent number: 12294379
    Abstract: A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: May 6, 2025
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Jae An
  • Patent number: 12294376
    Abstract: Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: May 6, 2025
    Assignee: Alphawave Semi, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Ayan Dutta
  • Patent number: 12294374
    Abstract: An integrated circuit (IC) includes a signal detection circuit having a signal detection circuit input and a signal detection circuit output. The IC further includes a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output. The IC also includes a comparator having a first comparator input and a second comparator input. The first comparator input is coupled to the reference voltage circuit output, and the second comparator input is coupled to the signal detection circuit output. The IC includes a clamp circuit having a clamp circuit input and a clamp circuit output. The clamp circuit input is coupled to the signal detection circuit, and the clamp circuit output is coupled to the reference voltage circuit output.
    Type: Grant
    Filed: May 30, 2024
    Date of Patent: May 6, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Adam Shook
  • Patent number: 12294377
    Abstract: A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: May 6, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 12289115
    Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 29, 2025
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Imanaka, Atsushi Motozawa
  • Patent number: 12289110
    Abstract: A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: April 29, 2025
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang