Patents Examined by Cassandra F Cox
  • Patent number: 11329636
    Abstract: A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Giacomo Cascio, Salvatore Angelo Della Fortuna
  • Patent number: 11316523
    Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Saurabh Singh, Jaimin Mehta, Sriram Balasubramanian, Anindya Bhattacharya
  • Patent number: 11313909
    Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: April 26, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Matthew R. Williamson, Sebastian Ahmed
  • Patent number: 11316519
    Abstract: A controller for a switched mode power converter (SMPC) module for use in a multiphase SCMP is disclosed, comprising: a signal generator, configured to generate a periodic signal and a clock, both having a frequency and a signal phase, and for controlling the switched mode power converter module; a first-clock and second-clock inputs configured to receive respective first-clock and second-clock signal having the frequency and respective first and second phases from neighbouring controllers; and wherein the signal generator comprises a phase adjustment circuit configured to adjust the phase of the periodic signal so as to be equidistant from the first and second phase, wherein the phase adjustment circuit determines an error signal in dependence on an offset between the phase and a mid-point between the first phase and the second phase, and a feedback circuit configured to adjust the phase in dependence on the error signal.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: April 26, 2022
    Assignee: NXP USA, INC.
    Inventors: Miguel Mannes Hillesheim, Marc Michel Cousineau, Eric Pierre Rolland, Philippe Goyhenetche, Guillaume Jacques Léon Aulagnier
  • Patent number: 11303289
    Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2? radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 12, 2022
    Assignee: Eridan Communications, Inc.
    Inventor: Richard W. D. Booth
  • Patent number: 11290113
    Abstract: A clock stretcher includes a digital DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The digital DLL corrects its delay speed at discrete times, during which it may be active. If the DLL delay line becomes slower while it is active, the modified clock signal would incur a glitch. The clock stretcher corrects for this glitch by using an increased hop code when a speed change occurs. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 29, 2022
    Assignee: SAMBANOVA SYSTEMS, INC.
    Inventors: Fahim ur Rahman, Sang-Min Lee, Jin-Uk Shin
  • Patent number: 11290117
    Abstract: A high-density logic circuit device low-frequency phase-locked loop system includes a digital logic input-output module; an internal clock; an instant-lock module; an instant-adjust error module; a high-speed count comparator; a multiplication factor-is-zero-state detect module with a reset function; a pulse generator; and a high-speed pulse generator. The high-speed count comparator includes a high-speed counter and a high-speed comparator. The input-output module receives an input frequency and transmits an output frequency. The instant lock module locks the output frequency in phase to a leading edge the input frequency within two internal propagation delays. The instant-adjust error module emits a pulse request until a last pulse is identified. The high-speed count comparator receives the pulse request and emits the output frequency. The pulse generators receive the input frequency and internal clock pulses and output a frequency-in pulse.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 29, 2022
    Inventor: Joseph Frank Kosednar, Jr.
  • Patent number: 11290114
    Abstract: A clock stretcher includes a DLL that derives delayed versions of an input clock signal. The clock stretcher has passive and stretching modes. It operates from a sensed power supply without intervening voltage regulation. In passive mode, it forwards input clock pulses to the clock stretcher output. The input clock pulses are delayed by fewer than 10 DLL delay line delay stages. In stretching mode, a combiner cyclically selects the delayed versions of the input clock signal to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. To enter passive mode, the clock stretcher tests if a passive mode entry threshold is met. The threshold includes two conditions: the hop code must be zero, and phase selection must have reached a wraparound point that may have been corrected for a delay line offset.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 29, 2022
    Assignee: SAMBANOVA SYSTEMS, INC.
    Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Jin-Uk Shin
  • Patent number: 11287474
    Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ha-Young Kim, Sung-We Cho, Dal-Hee Lee, Jae-Ha Lee
  • Patent number: 11290116
    Abstract: A control circuit of delay lock loop and a control method thereof are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector detects a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator sets an enable signal to an active state according to the trigger signal and sets the enable signal to a non-active state according to the comparison result. The control signal generator outputs a control clock to generate a control signal when the enable signal is in the active state.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: March 29, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Zong-Ying Ho, Chi-Hsiang Sun
  • Patent number: 11282566
    Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 11277141
    Abstract: A control circuit includes an oscillator configured to provide, to a digital load, a clock signal having an oscillation period that (i) depends on a supply voltage and (ii) is greater than a critical path delay of the digital load. The control circuit also includes a control module configured to provide the supply voltage to the digital load and the oscillator and adjust the supply voltage based on (i) a degree of a voltage difference between the supply voltage and a reference voltage and (ii) a degree of a phase difference between the clock signal and a reference clock such that the oscillator changes the oscillation period to reduce the degree of the phase difference between the clock signal and the reference clock.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 15, 2022
    Assignee: University of Washington
    Inventors: Visvesh S. Sathe, Xun Sun
  • Patent number: 11277123
    Abstract: A device for controlling transmission of electromagnetic waves according to the present disclosure includes: a conductor line which is positioned on a signal layer and through which electromagnetic waves received via an input terminal travel; a ground layer electrically separated from the signal layer through a dielectric layer and electrically grounded; a shunt via including a first end and a second end and connected to the conductor line through the first end; and a photoconductive semiconductor connected between the second end of the shunt via and the ground layer and having a dielectric state or a conducting state, based on an input of an optical signal, wherein the conductor line is electrically connected to the ground layer via the shunt via and the photoconductive semiconductor in the conducting state, thereby causing reflection of electromagnetic waves from the shunt via.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mikhail Nikolaevich Makurin, Anton Sergeevich Lukyanov, Elena Aleksandrovna Shepeleva, Artem Yurievich Nikishov, Artem Rudolfovich Vilenskiy
  • Patent number: 11277125
    Abstract: A drive circuit drives driven switches connected in parallel with one another. The driven switches each include first, second main, and main control terminals. When a potential difference of the main control terminal with respect to the second main terminal becomes greater than or equal to a threshold voltage, the flow of current between the first and second main terminals is permitted. At least two driven switches have different threshold voltages. The drive circuit includes, for each driven switch, an electrical path electrically connecting the second main terminal or a negative voltage supply, which is at a negative voltage lower than the potential of the second main terminal, to the main control terminal. The impedance of each of the electrical paths is set so the potential difference increased by electric charge flowing into the electrical path through a parasitic capacitance of the driven switch becomes less than the threshold voltage.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 15, 2022
    Assignee: DENSO CORPORATION
    Inventor: Kazunori Watanabe
  • Patent number: 11271550
    Abstract: A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Marcel A. Kossel, Pier Andrea Francese, Mridula Prathapan, Abdullah Serdar Yonar
  • Patent number: 11262777
    Abstract: A power supply circuit, includes: an N-channel depletion type output transistor connected between an input terminal of an input voltage and an output terminal of an output voltage; and an operational amplifier configured to control a gate of the output transistor so that a feedback voltage corresponding to the output voltage matches a reference voltage.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 1, 2022
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroki Inoue
  • Patent number: 11264972
    Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 1, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
  • Patent number: 11256285
    Abstract: A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Gyu Tae Park
  • Patent number: 11251661
    Abstract: An inductive power transmitter 2 comprising: a plurality of transmitter coils 7; a controller 8 configured to selectively energise the coils 7 in order to couple a receiver 3, the coils 7 selected being dependent on an orientation of the receiver 3, a power transfer optimisation algorithm, or a lookup table.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: February 15, 2022
    Assignee: Apple Inc.
    Inventor: Liang Chen
  • Patent number: 11251800
    Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 15, 2022
    Assignee: SOCIONEXT INC.
    Inventors: Hideki Kano, Tatsuya Sakae