Abstract: An integrated circuit (IC) includes a signal detection circuit having a signal detection circuit input and a signal detection circuit output. The IC further includes a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output. The IC also includes a comparator having a first comparator input and a second comparator input. The first comparator input is coupled to the reference voltage circuit output, and the second comparator input is coupled to the signal detection circuit output. The IC includes a clamp circuit having a clamp circuit input and a clamp circuit output. The clamp circuit input is coupled to the signal detection circuit, and the clamp circuit output is coupled to the reference voltage circuit output.

Abstract: Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.

Abstract: A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.

Abstract: A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.

Abstract: A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.

Abstract: A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die. Multi-output POL circuits may be used in conjunction with on-chip rail-selection and regulation circuitry to further improve efficiency.

Abstract: The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nth stage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nth stage may include an Nth fuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nth electronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal, and an Nth delay circuit coupled to the Nth e-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Nth e-fuse disconnecting. In this aspect, each of the stages of the failure event counting circuit may be configured to use the respective e-fuse to record a discrete failure event.

Abstract: Disclosed are a method and an apparatus of digital feedback based adaptive delay time control for a high efficiency active rectifier. According to the present invention, provided is an apparatus for digital feedback based adaptive delay time control, which adaptively compensates a driving delay of a switch by controlling a time of a delay circuit through a digital feedback-based compensation technique, and operate the switch at an appropriate timing in spite of changes in operation environments such as an input voltage and a load to increase the efficiency of an AC-DC rectifier.

Abstract: Disclosed is a quantum cryptography key distribution system. A receiving device of the system includes: a first single-photon detector outputting a data signal including a time-bin encoding pulse indicating a quantum signal; and a TDC receiving a predetermined reference timing signal and the data signal. The TDC is configured to determine a state of a time-bin qubit indicated by the time-bin encoding pulse based on a time difference between a first generation time point of a reference pulse included in the reference timing signal, and a second generation time point of the time-bin encoding pulse generated after the first generation time point.

Abstract: An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.

Abstract: A power distribution apparatus, comprising: a plurality of switches each operable to switch a respective power source of a plurality of power sources between a first input node of a first load and a second input node of a second load; a first power meter configured to determine a first power being delivered to the first input node from the plurality of power sources via the plurality of switches; a second power meter configured to determine the power consumption of the first load; and a control module configured to control the switches to distribute power between the first and second loads in dependence on the determined first power and the determined power consumption of the first load.

Abstract: An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

Abstract: A device for generating a sampling strobe, which controls a sampling device to sample an input signal, includes a phase shifter configured to phase shift an input clock to provide multiple phase shifted input clock signals; and aperture generating circuits configured to generate sampling clock signals from the phase shifted input clock signals, respectively, by adjusting duty cycles of the phase shifted input clock signals to provide sampling pulses having desired pulse widths, where for each sampling clock signal of the sampling clock signals, a rising edge and a falling edge of each sampling pulse originate from the same input edge of the input clock; and apply the sampling clock signals to interleaved samplers of the sampling device, respectively, for controlling sampling of the input signal by integrating according to the desired pulse widths of the sampling pulses, where the desired pulse widths correspond to sampling apertures.

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Abstract: Described is a frequency selective limiter (FSL) module comprising a cascade of an FSL and a functional limiter (e.g. a conventional semiconductor limiter comprising a PIN diode) with steady state limiting and power threshold values selected such the FSL module provides suppression of a spike leakage power and while still enabling frequency selective limiting.

Abstract: Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.

Abstract: In a switch device, an output voltage output by a microcomputer is input to one end of a resistor. A driving circuit switches a main switch on or off according to a resistor voltage at the other end of the resistor. When all of a plurality of specific voltages included in a plurality of output voltages output by the microcomputer are an output threshold or more, an AND circuit of an adjustment circuit reduces the resistor voltage.

Abstract: A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.

Abstract: A clock driver with duty cycle correction includes a first driver circuit, a second driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal and has parameters selected for a first frequency range of the clock input signal. The second driver circuit is nested with the first driver circuit and performs duty cycle correction on the clock input signal with parameters selected for a second frequency range of the clock input signal lower than the first frequency range. The correction logic circuit provides correction signals to a selected one of the first driver circuit and the second driver circuit. The clock driver provides a duty cycle corrected clock signal from the selected one of the first driver circuit and the second driver circuit based on a selected frequency range of the clock input signal.