Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Abstract: An electronic device and a method of controlling a slew rate for high-speed data communications are provided. The electronic device, according to an embodiment of the disclosure, includes a serializer configured to receive parallel data from another electronic device along with clock rate information, and convert the parallel data into serial data. The electronic device further includes a delay generator configured to generate a delay in the converted serial data using the clock rate information. The electronic device further includes a multiplexer configured to multiplex the converted serial data of the non-slew mode with the delayed data of the slew mode. The electronic device further includes a plurality of driver legs configured to receive the multiplexed data, and transfer the multiplexed data to the another electronic device. The electronic device further includes at least one of a voltage-controlled oscillator and a current-controlled oscillator configured to generate the clock rate information.

Abstract: A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die.

Abstract: An array substrate includes a base substrate including a first surface, a plurality of scanning signal lines disposed on the first surface, and at least two groups of shift register circuits disposed in a display area of the first surface. The first surface has the display area. Each scanning signal line extends along a first direction. Each group of shift register circuits includes a plurality of shift register circuits arranged along a second direction. Each shift register circuit is coupled to a scanning signal line. The first direction and the second direction intersect. At least one group of shift register circuits is disposed in a non-edge region of the display area. The shift register circuit disposed in the non-edge region of the display area is configured to transmit a scanning signal to the scanning signal line at both sides of the shift register circuit along the first direction.

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.

Abstract: A system and method for counting items are described. A photocell detects an item, after which a converter converts the generated digital signal to an audio signal that a computing device can recognize. Data from the counting of items is displayed on a user interface of the computing device and/or other visual interfaces.

Abstract: An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

Abstract: A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.

Abstract: A programmable delay structure includes at least one delay stage, each including an inverter connected between input and output nodes, a threshold voltage (VT)-programmable transistor, and a capacitor connectable to the output node through the transistor. During program mode operations, the transistor is programmed to have a low or high VT. During delay mode operation, the gate voltage is set between the low and high VTs. If the transistor has the low VT, the capacitor is connected to the output node and signal delay is increased. If the transistor has the high VT, the capacitor is not connected to the output node and signal delay is not increased. Illustrated embodiments include additional components for facilitating program mode and delay mode operations. Illustrated embodiments also include multiple delay stages where the output node of one stage is connected to the input node of the next. Also disclosed are associated operating methods.

Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

Abstract: The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wiring, and a case where it is preferable to connect the common signal terminals or the power supply terminals by circuits insulated from each other. The counter unit (10) is provided with a switching unit (15) that performs switching between a non-insulated circuit (16) that connects a plurality of common signal terminals (COMA, COMB, COMC) and/or a plurality of power supply terminals (IOV, IOG) by common wiring, and an insulated circuit (17) that connects the plurality of common signal terminals and/or the plurality of power supply terminals by circuits insulated from each other.

Abstract: A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form an anti-resonance tuning circuit has a first branch including a first inductance coupled to one of an IC die positive power supply conductor and an IC die negative power supply conductor, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

Abstract: Disclosed herein is an apparatus that includes: a first input node supplied with a first clock signal; a first clock path configured to output a delayed first clock signal, the first clock path including first and second delay elements coupled in series; a second clock path configured to output additional delayed first clock signal, the second clock path including third and fourth delay elements coupled in series; a first mixer circuit configured to interpolate the delayed first clock signal and the additional delayed first clock signal to reproduce an adjusted clock signal as the first clock signal; and a control circuit configured to control delay amounts of the first, second, third, and fourth delay elements with first, second, third, and fourth codes different from one another.

Abstract: A circuit for preventing false turn-on of a semiconductor switching device includes an active clamp circuit, a control circuit, a power amplifier circuit, and a suppression circuit. The control circuit is coupled to an input of the power amplifier circuit. An output of the power amplifier circuit is coupled to a gate of the semiconductor switching device. The active clamp circuit is configured to operate within a preset period when a voltage between the first end of the semiconductor switching device and a second end of the semiconductor switching device is greater than a preset voltage. The suppression circuit includes a controllable switch, which is configured to turn on after the operation of the active clamp circuit is completed, such that potential at the input of the power amplifier circuit is clamped to a fixed potential.

Abstract: A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

Abstract: Capacitively isolated current-loaded or current-driven charge pump circuits and related methods transfer electrical energy from a primary side to a secondary side over a capacitive isolation boundary, using a controlled current source to charge isolation capacitors with constant current, as opposed to current impulses, while maintaining output voltage within tolerance. The charge pump circuits provide DC-to-DC converters that can be used in isolated power supplies, particularly in low-power applications and in such devices as sensor transmitters that have separate electrical ground planes. The devices and methods transfer electrical energy over an isolated capacitive barrier in a manner that is efficient, inexpensive, and reduces electromagnetic interference (EMI).

Abstract: In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the refer

Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.

Abstract: Described is a frequency selective limiter (FSL) module comprising a cascade of an FSL and a functional limiter (e.g. a conventional semiconductor limiter comprising a PIN diode) with steady state limiting and power threshold values selected such the FSL module provides suppression of a spike leakage power and while still enabling frequency selective limiting.