Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.

Abstract: A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

Abstract: A delay control device for controlling a delay circuit includes an oscillator, a counter, and an output control circuit. The oscillator generates an internal clock signal according to an external clock signal. The counter generates an accumulative signal according to the internal clock signal. The counter is selectively reset by the external clock signal. The output control circuit generates a delay indication signal according to the accumulative signal. The delay time of the delay circuit is adjusted according to the delay indication signal.

Abstract: The present disclosure concerns a device for supplying an adjustable current configured to supply discrete values of the current belonging to different current ranges, with a pitch between two successive discrete values determined by that of said ranges to which each of the two successive discrete values belongs.

Abstract: First and second paths (I,II) are connected in parallel between an input terminal (IN) and an output terminal (OUT). A high-pass filter (HPF) is provided in the first path (I). A low-pass filter (LPF) is provided in the second path (II). A switch (SW1-SW4) connects one of the high-pass filter (HPF) and the low-pass filter (LPF) to the input terminal (IN) and the output terminal (OUT) and disconnects the other. A transmission line (TL1,TL2) is provided on the first and second paths (I,II) respectively. A line length of the transmission line (TL1,TL2) is adjusted such that a resonance caused due to circuit constants of the high-pass filter (HPF) and the low-pass filter (LPF) and capacitance obtained when the switch (SW1-SW4) is OFF is shifted to a communication frequency band.

Abstract: The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.

Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.

Abstract: A circuit for controlling a switch of a power converter includes a first clock signal generator configured to generate a first clock signal and a switching signal generator configured to generate a switching signal to control the switch of the power converter based on the first clock signal. The circuit further includes error detection circuitry configured to output an error indication and a second clock signal generator configured to generate, in response to the error indication, a second clock signal that comprises an edge of a clock cycle of the second clock signal that corresponds to when the switching signal deactivates the switch of the power converter plus a time delay. The switching signal generator is configured to generate the switching signal to control the switch of the power converter further based on the second clock signal in response to the error indication being output by the error detection circuitry.

Abstract: A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes a first inverter configured to selectively propagate the signal along the first signal path, a second inverter configured to selectively propagate the signal along the second signal path, and a third inverter configured to selectively propagate the signal from the first signal path to the second signal path. Each of the first and third inverters has a tunable selection configuration corresponding to greater than three output states.

Abstract: A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal.

Abstract: A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.

Abstract: A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.

Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.

Abstract: A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

Abstract: In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

Abstract: Methods and devices for determining integrated circuit (IC) device degradation over time are provided. Transistors are the basic building blocks of IC devices. The degradation of the transistors in IC devices over time leads slowly to decreased switching speeds. To monitor the condition of an IC device as it ages, oscillator circuitry operating at switching frequencies of various circuits in the IC device may be included and monitored for changes in switching frequency over time. A degraded condition of the IC device may be determined when the change in switching frequency exceeds a threshold value.