Patents Examined by Charles Bowers
  • Patent number: 6740580
    Abstract: A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: May 25, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Chyi S. Chern, Mei Sheng Zhou
  • Patent number: 6664144
    Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: December 16, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Hisashi Ohtani
  • Patent number: 6645825
    Abstract: An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: November 11, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chin Kun Lan, Ting Chun Wang, Tong-Hua Kuan, Ying-Lang Wang
  • Patent number: 6593245
    Abstract: A method for plasma etching of silicon nitride using a mixture of trifluoromethane and oxygen in a ratio of approximately 8 to 1 to selectively etch silicon nitride in preference to silicon dioxide and photoresist, resulting in critical dimension gain.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: July 15, 2003
    Assignee: Advanced Micro Devices
    Inventor: Maria Chan
  • Patent number: 6573118
    Abstract: The surface of the semiconductor wafer includes a silicon substrate containing first-type dopants, a well of first-type dopants positioned in a predetermined region on the substrate, a photo diode positioned on the semiconductor wafer and comprising an active region positioned on the surface of the well, the active region being used to form a MOS transistor of second-type dopants, and an insulation layer positioned on the surface of the substrate surrounding a predetermined photo sensor, the photo sensor positioned beside the well. A first ion implantation process is performed to form a first doped region of second-type dopants on the surface of the photo sensor. A second ion implantation process is then performed to form a second doped region of second-type dopants inside the photo sensor.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: June 3, 2003
    Assignee: United Microelectronics Corp.
    Inventor: Jui-Hsiang Pan
  • Patent number: 6531036
    Abstract: A method for fabricating sub-millimeter sized parts uses electrodes created from patterned silicon wafers for electric-discharge machining (EDM), in which an electric discharge is generated between a patterned electrode and a conductive workpiece. Workpiece material corresponding to the electrode pattern is removed by electroerosion, and the remaining workpiece contains the desired part. Electrodes are formed by etching stepped patterns in silicon wafers and depositing a thin metallic layer on the wafer. The resulting electrode is used in an EDM machine, and an inverse pattern is produced in the part. Alternately, the silicon wafer pattern is filled by a metal to produce a metal electrode with an inverse pattern. The wafer is removed from the metal, and the metal is used in an EDM machine. The resulting part has the same pattern as the silicon wafer used to create the metal electrode.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: March 11, 2003
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Rudolf Leitgeb, Jurgen Stampfl, Yih-Lin Cheng, Friedrich Prinz
  • Patent number: 6465892
    Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: October 15, 2002
    Assignees: Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventor: Tadatomo Suga
  • Patent number: 6465278
    Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the Semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: October 15, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Ernest J. Russell
  • Patent number: 6458677
    Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the sequential formation of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer using an in-situ deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. To avoid exposure to ambient atmosphere, the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer are sequentially formed using either a PECVD or a SACVD process.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: October 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn M. Hopper, David K. Foote, Bharath Rangarajan
  • Patent number: 6458715
    Abstract: A target semiconductor device can be obtained stably by reforming an insulating film and a semiconductor. In a process of manufacturing a semiconductor device, at least one of the semiconductor and the insulating film is reformed after an annealing process for annealing the semiconductor at a temperature ranging from 20 to 400° C. in the atmosphere containing a gas of water (H2O) with a partial pressure from 1 Torr to a saturated vapor pressure for an annealing time ranging from 15 seconds to 20 hours.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: October 1, 2002
    Assignee: Sony Corporation
    Inventors: Naoki Sano, Masaki Hara, Mitsunobu Sekiya, Toshiyuki Sameshima
  • Patent number: 6455326
    Abstract: An improved sputtering method for sputter deposition from non-conducting metal oxide, ceramic, and ferroelectric targets is disclosed. Enhancements in deposition rate and composition control have been demonstrated using a pulsed DC sputtering method using a power supply in the frequency range of 100 to 250 KHz and a low frequency RF sputtering method using a power supply in the range of 200 to 500 KHz. The enhancement in composition control comes from an improvement in the sticking efficiencies of the volatile components in ferroelectric films. The low frequency and/or pulsed DC supplies provide lead content control for optimizing ferroelectric performance in pressure regimes that favor better cross wafer composition and thickness uniformity in PVD (Physical Vapor Deposition) sputtering tools.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: September 24, 2002
    Assignee: Ramtron International Corporation
    Inventor: Brian Eastep
  • Patent number: 6448110
    Abstract: A method for forming a back-to-back dual-chip package and package formed are disclosed. In the method, a first IC chip is bonded in its inactive surface to an inactive surface of a second IC chip, while solder balls planted on the active surfaces of both chips. One of the chips is connected to lead fingers of a lead frame by the solder balls. The dual-chip assembly together with the lead fingers are then encapsulated in an insulating material for protecting the chips while exposing substantially the solder balls on the IC chip that was not connected to the lead fingers. The encapsulated assembly can then be connected to an outside circuit, such as a printed circuit board, by forming the exposed finger leads for soldering and by fusing the solder balls to the outside circuit. The present invention novel method and device formed advantageously utilize existing chip design for achieving a high density device at a low cost.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: September 10, 2002
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Chieh Chen, Chun-Liang Chen
  • Patent number: 6448666
    Abstract: The present invention relates to a method for forming an insulating film with a low relative dielectric constant. A method for forming an insulating film in terms of a plasma chemical vapor deposition, characterized in that a Si supply gas, an oxygen supply gas, and a fluorine supply gas are used a material gas to form said insulating film, and said insulating film is formed under a film forming condition that a density of said insulating film to be formed is equal to or more than 2.25 g/cm3.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: September 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kudo, Rika Shinohara
  • Patent number: 6448147
    Abstract: As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a #-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: September 10, 2002
    Inventor: Masahiro Komuro
  • Patent number: 6444593
    Abstract: A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: September 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Richard J. Huang, Guarionex Morales
  • Patent number: 6444480
    Abstract: A semiconductor device fabrication apparatus includes a thermal treatment device for thermally processing a semiconductor substrate, a first oxygen monitor for monitoring the density of oxygen in said thermal treatment device, a load-lock chamber separably coupled to said thermal treatment device for housing the semiconductor substrate before thermal treatment thereof by said thermal treatment device, and a second oxygen monitor for monitoring the density of oxygen in said load-lock chamber. First, the semiconductor substrate is introduced into the load-lock chamber, and then the load-lock chamber is evacuated. Thereafter, the density of oxygen in the load-lock chamber is measured by the second oxygen monitor, and the thermal treatment device is evacuated, after which the density of oxygen in the thermal treatment device is measured by the first oxygen monitor.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: September 3, 2002
    Assignee: Sony Corporation
    Inventor: Masaki Saito
  • Patent number: 6444579
    Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: September 3, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 6437408
    Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: August 20, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jiaw-Ren Shih, Shui-Hung Shen, Jian-Hsing Lee, Chrong Jung Lin
  • Patent number: 6436818
    Abstract: Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: August 20, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Hu, Pai-Hung Pan, Er-Xuan Ping, Randhir P. S. Thakur, Scott DeBoer
  • Patent number: 6436761
    Abstract: There is provided a method for manufacturing semiconductor memory devices includes the steps of; forming, for example, an N-type MOS transistor as a memory-cell selecting transistor on a P-type silicon substrate beforehand; forming, as a capacitive-element manufacturing step, an HSG on a first amorphous silicon film which provides a lower electrode; and diffusing an impurity into this HSG and then removing a surface layer of the HSG.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: August 20, 2002
    Assignee: NEC Corporation
    Inventors: Yoshihiro Harada, Nobuyuki Yamanishi