Patents Examined by Charles Bowers
  • Patent number: 6387794
    Abstract: An electrode structure for a semiconductor device and a method for forming the electrode structure, and a mounted body including the semiconductor device are provided in which the semiconductor device can be easily connected to a circuit board with high reliability. An aluminum electrode is formed on an IC substrate. A passivation film is formed on the IC substrate so as to cover the peripheral portion of the aluminum electrode. A bump electrode is formed on the aluminum electrode by a wire bonding method. An aluminum oxide film is formed on the surface of the aluminum electrode that is exposed around the bump electrode. A conductive adhesive is applied as a bonding layer to the tip portion of the bump electrode of the semiconductor device by a transfer method or a printing method. The semiconductor device is aligned in the face-down state in such a manner that the bump electrode abuts on a terminal electrode of a circuit board, and is provided on a circuit board.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: May 14, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshihiro Bessho
  • Patent number: 6387823
    Abstract: A method for controlling a deposition process, includes providing a wafer in a chamber of a deposition tool, the deposition tool being adapted to operate in accordance with a recipe; providing reactant gases to the chamber, the reactant gases reacting to form a layer on the wafer; allowing exhaust gases to exit the chamber; measuring characteristics of exhaust gases; and changing the recipe based on the characteristics of the exhaust gases. A deposition tool includes a chamber, a gas supply line, a gas exhaust line, a gas analyzer, and a controller. The chamber is adapted to receive a wafer. The gas supply line is coupled to the chamber for providing reactive gases. The gas exhaust line is coupled to the chamber for receiving exhaust gases. The gas analyzer is coupled to the gas exhaust line and adapted to determine characteristics of the exhaust gases. The controller is adapted to control the processing of the wafer in the chamber based on the characteristics of the exhaust gases.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: May 14, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Sonderman, Anthony J. Toprac
  • Patent number: 6387756
    Abstract: The present invention relates to a method of manufacturing a non-volatile semiconductor device having a structure in which layers of a first insulating film, a first polysilicon layer, a second insulating film and a second polysilicon layer are formed, in this order, on a semiconductor substrate; which comprises the steps of forming the first insulating film on the semiconductor substrate and thereafter forming the first polysilicon layer; patterning the first polysilicon layer; performing a heat treatment in hydrogen atmosphere; forming the second insulating film; forming the second polysilicon layer; and patterning the second polysilicon layer. In accordance with the present invention, a non-volatile semiconductor device having excellent hold characteristics and only a small dispersion of element characteristics can be manufactured.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: May 14, 2002
    Assignee: NEC Corporation
    Inventor: Satoru Muramatsu
  • Patent number: 6387765
    Abstract: A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: May 14, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vijai Kumar Chhagan, Yelehanka Ramachandramurthy Pradeep, Mei Sheng Zhou, Henry Gerung, Simon Chooi
  • Patent number: 6387741
    Abstract: Silicon layers 2a, 2b comprised of different thicknesses are formed concurrently so as to be isolated from each other while a silicon oxide layer 1 serving as a foundation layer is controlled to be free from hollows by implanting ions only into a field silicon oxide layer 5a comprised of a thick film thickness among field silicon oxide layers 5a, 5b to be used for separating circuit elements, and thereby altering etching rates of the field silicon oxide layers 5a, 5b.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: May 14, 2002
    Assignee: Asahi Kasei Microsystems Co., Ltd.
    Inventor: Michihiro Kawano
  • Patent number: 6387789
    Abstract: Method for fabricating a semiconductor device, including the steps of (1) forming a gate insulating film, a silicon layer, and an insulating film on a substrate in succession, (2) selectively removing a portion of the insulating film on which a gate electrode is to be formed, (3) forming first sidewalls at sides of the insulating film having the portion removed therefrom, (4) forming silicide on a surface of the exposed silicon, (5) forming a cap insulating film on the silicide and the first sidewalls, (6) removing the insulating film, and (7) using the cap insulating film as a mask in removing the exposed silicon layer, to form the gate electrode.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: May 14, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jong Kwan Kim
  • Patent number: 6387713
    Abstract: To offer a microstructure fabrication apparatus capable of realizing MEMS and a Rugate Filter excellent in performance characteristics by patterning a thick functional material film in high aspect ratio with a simple and practical manufacturing method. A Si layer is employed for a mask pattern. The advantages of the Si layer are withstood a process conducted at high temperature for forming a PZT layer, which is the functional material layer, patterned in high aspect ratio, and achieves excellent process consistency for the whole manufacturing processes of the microfabrication. A trench or a gap is formed with the mask pattern deeper than the desired PZT layer. The PZT layer, or functional material layer (films) is formed on the whole surface including the bottom of the concave part of the mask pattern. The PZT layer deposited on the mask pattern is removed with the mask pattern itself, and selectively remains the pattern of the PZT layer, thereby obtaining a pattern of the desired functional material layer.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: May 14, 2002
    Assignee: Sony Corporation
    Inventor: Masaki Hara
  • Patent number: 6387755
    Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: May 14, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Timothy J. Thurgate, Scott D. Luning
  • Patent number: 6387732
    Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: May 14, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6387781
    Abstract: Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow columns of metal silicide embedded in a matrix of single crystal, epitaxially grown silicon. Higher substrate temperatures and lower deposition rates yield larger columns that are farther apart while more silicon produces smaller columns. Column shapes and locations are selected by seeding the substrate with metal silicide starting regions. A variety of 3-dimensional, exemplary electronic devices are disclosed.
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: May 14, 2002
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Robert W. Fathauer
  • Patent number: 6387763
    Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: May 14, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Pio, Paola Zuliani
  • Patent number: 6387731
    Abstract: The present invention provides a ball grid array (“BGA”) assembly and process of manufacturing for reducing warpage caused by the encapsulation of the associated semiconductor chip. The assembly and process includes coupling a substrate between a semiconductor chip and a BGA structure; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the semiconductor chip.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: May 14, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Richard Wensel, Scott Gooch
  • Patent number: 6387828
    Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 14, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Richard H. Lane, Phillip G. Wald
  • Patent number: 6387825
    Abstract: This invention describes improved apparatus and methods for spin-on deposition of thin films applicable to the manufacture of semiconductor devices. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: May 14, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lu You, Dawn Hopper, Richard J. Huang
  • Patent number: 6387734
    Abstract: An insulating layer (3) is formed on a Si wafer (1). An opening portion is made in this insulating layer (3), and subsequently a rerouting layer (2) is formed. Next, a resin layer (4) is formed on the rerouting layer (2). The resin layer (4) is then cured so that the rerouting layer (2) and a Cu foil (5) are bonded to each other through the resin layer (4). Thereafter, a ring-like opening portion (4a) is made in the resin layer (4), and a Cu plating layer (8) is formed inside this opening portion (4a).
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: May 14, 2002
    Assignee: Fujikura Ltd.
    Inventors: Masatoshi Inaba, Takanao Suzuki, Tadanori Ominato, Masahiro Kaizu, Akihito Kurosaka
  • Patent number: 6387822
    Abstract: A method and apparatus for resist strip. Wafers (108) with a patterned resist formed thereon are placed in a carrier (104) in a process chamber (102). An ozonated deionized water mist (120) is sprayed on the surface of wafer (108). The ozonated deionized water mist (120) strips the resist and removes the resist residue without the use of hazardous chemicals. The ozonated deionized water mist (120) may be formed in an atomizer that mixes deionized water (116) with ozone (118). The ozonated deionized water mist (120) is then sprayed onto the wafers (108) while the wafers are being rotated.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: May 14, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Neal T. Murphy, Claire Ching-Shan Jung, Danny F. Mathews
  • Patent number: 6387762
    Abstract: A method of manufacturing a ferroelectric memory device which has a gate structure constituted by a ferroelectric layer and a conductor layer stacked on a semiconductor substrate. The method includes steps of forming the gate structure section by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities thereby to form a pair of impurity diffused layers.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: May 14, 2002
    Assignee: Rohm Co., LTD
    Inventors: Hidemi Takasu, Takashi Nakamura
  • Patent number: 6387793
    Abstract: A method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium on a substrate containing, preferably, III-V semiconductor circuits. The multilayer UBM pad, preferably comprising a 0.02 to 0.05 micrometer thick layer of titanium, a 0.5 to 1.0 micrometer thick layer of nickel and a 0.1 to 0.2 thick layer of gold. The protective film with the thickness of preferably 0.5 to 40 micrometer comprises a photoresist. After the solder has been electroplated, the protective film is removed, preferably by dry etching or with a solvent. The titanium film serves a dual function of being a membrane for electroplating of the solder and of being a non-wettable dam for wetting back of the plated solder. The titanium film with the thickness of 200 to 1,000 Angstroms is preferably deposited by evaporation.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: May 14, 2002
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Phillip H. Lawyer
  • Patent number: 6387712
    Abstract: In a film structure comprising a ferroelectric thin film formed on a substrate, the ferroelectric thin film contains a rare earth element (Rn), Pb, Ti, and O in an atomic ratio in the range: 0.8≦(Pb+Rn)/Ti≦1.3 and 0.5≦Pb/(Pb+Rn)≦0.99, has a perovskite type crystal structure, and is of (001) unidirectional orientation or a mixture of (001) orientation and (100) orientation. The ferroelectric thin film can be formed on a silicon (100) substrate, typically by evaporating lead oxide and TiOx in a vacuum chamber while introducing an oxidizing gas therein.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: May 14, 2002
    Assignee: TDK Corporation
    Inventors: Yoshihiko Yano, Takao Noguchi
  • Patent number: 6387773
    Abstract: A method for fabricating trenches for storage capacitors of DRAM semiconductor memories by plasma etching semiconductor substrates, includes fabricating a partial trench region with a cross-sectional profile deviating from essentially constant toward a larger cross-sectional profile. A surface of the partial trench region is passivated and the etching/passivating step is continued periodically, in order to fabricate further partial trench regions, until a predetermined overall trench depth has been reached.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: May 14, 2002
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt