Abstract: In the semiconductor device disclosed in the present invention, the well regions in the internal circuit comprise high-impurity-concentration regions 4 and 5 as lower layers and low-impurity-concentration regions 2 and 3 as upper layers, and the well regions in the I/O-protective circuit comprise only low-impurity-concentration regions 11 and 12. As a result, there can be realized an internal circuit having good latch-up resistance and an I/O-protective circuit having good static surge resistance.

Abstract: A system and apparatus is provided for preventing damage to gate oxide due to ultraviolet radiation associated with semiconductor processes. Included is a substrate and a gate formed on the substrate. The gate includes a gate material layer and a gate oxide layer stacked on the substrate. A pair of spacers are situated on opposite sides of the gate. Deposited over the gate and the spacers is an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate. Finally, at least one metal and intermetal oxide layer is positioned over the ultraviolet radiation blocking material. In an alternate embodiment, instead of the ultraviolet radiation blocking material being deposited over the gate and the spacers, the spacers are constructed from an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level.

Abstract: A semiconductor device comprises a first insulating film formed over a semiconductor substrate, a second insulating film formed on the first insulating film, a contact plug made of a conductive material vertically penetrating the first and second insulating films and extending on the second insulating film, and a conductor film in contact with the upper surface of the contact plug and part of the second insulating film. This construction makes it possible to form minute via-holes in a mass-production line without increasing parasitic capacity, increasing the number of manufacturing steps, and generating defects.

Abstract: Methods for fabricating memory devices having a multi-dot floating gate ensuring a desirable crystallization of a semiconductor film without ruining the flatness of the surface of the polycrystallized silicon layer and a tunnel oxide film, allowing desirable semiconductor dots to be produced, and allowing production of the memory devices having a multi-dot floating gate with ease and at low costs even when a substrate is made of glass or plastic.

Abstract: A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

Abstract: A strip-like first insulating layer is formed on a glass substrate, and a second insulating layer is formed on the first insulating layer. Furthermore, an island-like semiconductor layer is formed on the second insulating layer. The island-like semiconductor layer is crystallized by irradiation with laser light through both surfaces of the glass substrate.

Abstract: A process for the thermal annealing of implantation-doped silicon carbide semiconductors in a gas stream brings practically no carbon to the silicon carbide semiconductor. In one embodiment, a container, a carrier, radiation shields and a baseplate are composed of a metal or a metal compound such as, for example, tantalum or tantalum carbide, at least at locations which come into contact with the gas stream.

Abstract: Disclosed is a method for stacking semiconductor chips, including positioning a first chip and manipulating a second chip to a distance above the first chip that is no greater than a selected distance, and releasing the second chip to drop into a stacked configuration on the first chip. The selected distance is such as to avoid damage to either of the chips. Embodiments are disclosed for setting the drop distance of the second chip within the selected distance.

Abstract: There is disclosed a heat treatment method for a silicon wafer in which the silicon wafer is heat treated in a reducing atmosphere through use of a rapid heating/rapid cooling apparatus. The silicon wafer is heat treated for a period of 1 to 60 seconds at a temperature in the range of 1200° C. to the melting temperature of silicon. The heat treatment method can reduce the density of COPs and micro-defects which serve as nuclei of oxidation induced stacking faults at the surface of the silicon wafer.

Abstract: A process for manufacturing a resistive structure that has a polysilicon strip laid above a semiconductor substrate is presented. The process begins by using a mask to cover the polysilicon strip. Then, several apertures are made in the mask until portions of the semiconductor strip are uncovered. Next, a dopant is implanted in the polysilicon semiconductor strip through the apertures. Finally, the resistive structure is subjected to a thermal process for diffusing the dopant in such a way to obtain a variable concentration profile in the semiconductor strip.

Abstract: A method of fabricating a device is provided. A shadow mask is positioned in a first position over a substrate. A first process is performed on the substrate through the shadow mask. After the first process is performed, the shadow mask is moved to a second position over the substrate, measured relative to the first position. After the shadow mask is moved to the second position, a second process is performed on the substrate through the shadow mask.

Abstract: A process for eliminating an interface layer between a poly plug and a hemispherical silicon grain. A substrate comprising a conductive plug and a storage node opening is provided, and the storage node opening is located on the conductive plug. Then, a first conductive layer is formed conformably over the inside surface of the storage node opening and a hemispherical silicon grain layer is formed on the first conductive layer. Next, the hemispherical silicon grain layer and the first conductive layer is implanted and the substrate is annealed. The re-arrangement and re-crystallization of the interface layer can greatly reduce the resistance of the node contact.

Abstract: A method for forming a non-single-crystal semiconductor thin film and a photovoltaic device using an apparatus, which has a film deposition chamber with a film-forming space surrounded by a film deposition chamber wall and a belt-like substrate. An external chamber surrounding the deposition chamber wall is provided in the apparatus. While the belt-like substrate is moved in a longitudinal direction, a film-forming gas is introduced through a gas supply device into the film-forming space and microwave energy is radiated from a microwave applicator into the film-forming space to induce a microwave plasma, and thereby form a non-single-crystal semiconductor thin film on a surface of the belt-like substrate. A cooling mechanism and a temperature-increasing mechanism covering a part of an outside surface of the deposition chamber wall provide temperature control.

Abstract: In a method of determining a linewidth of a polysilicon line formed by a lithographic process, a polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. A related test structure is also disclosed.

Abstract: A flip-chip device and process for fabricating the device employs a multilayer encapsulant that includes a first portion encapsulant having a coefficient of thermal expansion of at most 30 ppm/° C. and an elastic modulus of 2-20 GPa and a second portion comprising a polymer flux having a coefficient of thermal expansion that may exceed 30 ppm/° C.

Abstract: A manufacturing process OF a thin film transistor is provided, in which occurrence of a dry spot and occurrence of an etch residue of an ohmic contact layer (n+a-Si:H film) due to the dry spot are prevented in photoengraving process for patterning a semiconductor layer and the ohmic contact layer into an island, without any further treatment by any other apparatus. After forming the a-Si:H film 4a which forms the semiconductor layer of the TFT and the n+a-Si:H film 5a which forms the ohmic contact layer, a N2 gas plasma discharge is continuously performed using the same plasma CVD apparatus, thereby forming a very thin silicon nitride film 6 having a hydrophilic property on a surface layer of the n+a-Si:H film 5a.

Abstract: A process for the selective passivation of the channel walls of a channelled ink-jet printhead component by the chemical vapor deposition of a passivant coating, the process comprising mounting the component in a support in registration with a datum location therein, the support having masking means for masking selected areas of the component, and depositing the passivant coating on unmasked portions of the channel walls.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device in which a hemispherical grain size of an inner and an outer wall surfaces of a cylindrical member is uniform to promote the increase of surface areas and to prevent short-circuit between the adjacent cylindrical members. This is achieved (i) by removing an amorphous silicon originally grown layer or (ii) by suppressing the function of the originally grown layer.

Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed.