Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a fixed magnetic layer, a tunnel barrier layer on the fixed magnetic layer, and a free magnetic layer formed on the tunnel barrier layer. A boron-segregating layer is formed directly on the free magnetic layer. The memory stack is etched into a pillar. A top electrode is formed over the pillar.

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

Abstract: Provided are methods and systems for providing oxygen doped silicon carbide. A layer of oxygen doped silicon carbide can be provided under process conditions that employ silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the oxygen doped silicon carbide. The one or more radical species can be formed in a remote plasma source.

Abstract: A method of separating a wafer including rows of light emitting devices is described. Dicing streets are provided on the wafer such that a respective one of the dicing streets is provided between each of the rows of light emitting devices on the wafer. The wafer is broken along a first one of the dicing streets to separate a first portion of the wafer from a remaining portion of the wafer. The first portion of the wafer includes more than one of the rows of light emitting devices. The first portion of the wafer is broken along a second one of the dicing streets to separate a second portion of the wafer from the first portion of the wafer.

Abstract: Method for positioning and orienting a first object relative to a second object. The method includes positioning a near field transducer having an aperture on the first object, and directing a laser light toward the aperture of the near field transducer on the first object to create an evanescent wave on the other side of the aperture. Positioning a sensor on the second object for detecting the effervescent wave from the near field transducer. Providing an algorithm, and using information obtained from the sensor on the second object in the algorithm to control a nanopositioning system to position one of the first object and the second object in a desired position and orientation relative to the other one of the first object and the second object.

Abstract: A method and apparatus for filling one or more gaps created during manufacturing of a feature on a substrate by: providing a bottom area of a surface of the one or more gaps with a first reactant; providing a second reactant to the substrate; and, allowing the first reactant to initiate reaction of the second reactant in the bottom area of the surface in a stoichiometric ratio of one molecule of the first reactant to multiple molecules of the second reactants leaving a top area of the surface of the one or more gaps which was not provided with the first reactant initially substantially empty.

Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

Abstract: Disclosed are method embodiments for forming an integrated circuit (IC) structure with at least one first-type FINFET and at least one second-type FINFET, wherein the first-type FINFET has a first replacement metal gate (RMG) adjacent to a first semiconductor fin, the second-type FINFET has a second RMG adjacent to a second semiconductor fin, and the first RMG is in end-to-end alignment with the second RMG and physically and electrically isolated from the second RMG by a dielectric column. The method embodiments minimize the risk of the occurrence defects within the RMGs by forming the dielectric column during formation of the first and second RMGs and, particularly, after deposition and anneal of a gate dielectric layer for the first and second RMGs, but before deposition of at least one of multiple work function metal layers. Also disclosed herein are IC structure embodiments formed according to the above-described method embodiments.

Abstract: A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. The source coupling structure separated from the cell structure may include alternately stacked second conductive patterns and second interlayer insulating layers. The source discharge transistor may be coupled to the source coupling structure.

Abstract: The invention teaches a system and method for reducing energy consumption in commercial buildings. The invention provides development of certain mechanical cooling profiles and use of such profiles in an automated optimization method. Outputs communicate with the building management system of the commercial building, and regulate the cooling system during a season when the building activates the cooling system. Various embodiments are taught.

Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.

Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.

Abstract: A device includes a first channel region and a first gate structure formed over the first channel region. A first source/drain region is adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers. A gradient of decreasing concentration of the first dopant is one decade for every 5.5 to 7.5 nanometers deeper than the first concentration.

Abstract: Electrical components may be packaged using system-in-package configurations or other component packages. Integrated circuit dies and other electrical components may be soldered or otherwise mounted on printed circuits. A layer of encapsulant may be used to encapsulate the integrated circuits. A shielding layer may be formed on the encapsulant layer to shield the integrate circuits. The shielding layer may include a sputtered metal seed layer and an electroplated layer of magnetic material. The electroplated layer may be a magnetic material that has a high permeability such as permalloy or mu metal to provide magnetic shielding for the integrated circuits. Integrated circuits may be mounted on one or both sides of the printed circuit. A temporary carrier and sealant may be used to hold the encapsulated integrated circuits during electroplating.

Abstract: A semiconductor device includes an n+-type source region having an impurity concentration higher than that of an n-type source region, formed in a surface layer of a p-type SiC layer and a p-type base region, farther on an outer side than the n-type source region, and contacting the n-type source region; an n-type region and an n+-type region having an impurity concentration higher than that of the n?-type SiC layer, formed in a portion of the n?-type SiC layer between p-type base regions and p-type SiC layers; and a second n-type region under the p-type base region and of a size smaller than that of the p-type base region, whereby low on-resistance and precision of the threshold voltage Vth are enhanced, increasing quality and enabling improved resistance to dielectric breakdown of the gate insulating film and resistance to breakdown.

Abstract: A method of transferring a thin film includes: providing a first element structure, wherein the first element structure includes a first substrate and a functional film layer formed on the first substrate; completely removing the first substrate, wherein steps of the completely removing the first substrate includes: conducting an etching step to erode the first substrate, and conducting a grinding step to planarize the eroded first substrate; and after completely removing the first substrate, attaching the functional film layer on a second substrate to form a second element structure.

Abstract: Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein the substrate forms part of an electronic component. The heat dissipating structures are formed from graphene, with advantage being taken of the high thermal conductivity of graphene. The graphene (e.g., in flake form) is attached to a diazonium molecule, and further, the diazonium molecule is utilized to attach the graphene to material forming the substrate. A surface of the substrate is treated to comprise oxide-containing regions and also oxide-free regions having underlying silicon exposed. The diazonium molecule attaches to the oxide-free regions, wherein the diazonium molecule bonds (e.g., covalently) to the exposed silicon. Attachment of the diazonium plus graphene molecule is optionally repeated to enable formation of a heat dissipating structure of a required height.

Abstract: A light emitting device comprises: an LED chip having a quantum well structure and a light emitting layer made of a gallium nitride compound semiconductor; a first transparent material covering the LED chip; a second transparent material for protecting the LED chip and the first transparent material; and a phosphor for absorbing a part of the light from the LED chip and emitting a light having a wavelength different from the light from the LED chip; wherein the phosphor is included in second transparent material, and the light from the LED chip and the light from said phosphor are mixed to make a white light.

Abstract: A kind of growth method of Fe3Nin the MOCVD system, comprising following process: 1) make the surface nitridation of sapphire substrate; 2) pump in carrier gas N2, ammonia and organic gallium sources, and grow low temperature GaN buffer on substrate; 3) raise temperature and grow the GaN supporting layer; 4) pump in FeCp2 as Fe sources, then grow Fe3N on the GaN supporting layer; the Fe3N granular films and the Fe3N single crystal films are obtained.

Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.