Abstract: Various methods and structures for fabricating a strained semiconductor fin of a FinFET device. A strained semiconductor fin structure includes a substrate, a semiconductor fin disposed on the substrate, the semiconductor fin having two fin ends, and a stressor material cladding wrapped around a portion of each of the two fin ends forming a strained semiconductor fin that includes at least one strained channel fin having stressor cladding wrapped around at least one end of the strained channel fin thereby straining the at least one strained channel fin. The stressor cladding can be a compressive nitride stressor to compressively strain a compressively strained silicon germanium fin. The stressor cladding can be a tensile nitride stressor to tensily strain a tensily strained silicon fin.

Abstract: Mass transfer of micro structures are effected from one substrate to another using adhesives. In the context of an integrated micro LED display, a micro LED array is fabricated on a native substrate and corresponding CMOS pixel drivers are fabricated on a separate substrate. The micro LED substrate (e.g., sapphire) and the CMOS substrate (e.g., silicon) may be incompatible. For example, they may have different thermal coefficients of expansion which make it difficult to bond the micro LEDs to the pixel driver circuitry. The micro LED array is transferred to an intermediate substrate (e.g., silicon) by use of an adhesive. This intermediate substrate may be used in a process of bonding the micro LED array to the array of pixel drivers. The intermediate substrate is separated from the micro LED array by releasing the adhesive.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa2<Bb×Ob2.

Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

Abstract: A pressure detecting includes a plurality of sensing cells arranged a plurality of rows and columns, each of the plurality of sensing cells including a pressure sensing element and a selection transistor. First driving signal lines are disposed in the rows, and the first driving signal lines are connected to the selection transistors of a first portion of the plurality of sensing cells in a respective row. Second driving signal lines are disposed in a portion of the plurality of rows, and the second driving signal lines are connected to the selection transistors of a second portion of the plurality of sensing cells in a respective row. First and second driving circuits are respectively connected to the first driving signal lines the second driving signal lines.

Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

Abstract: A semiconductor device includes a first semiconductor layer formed of a compound semiconductor, provided over a substrate; a second semiconductor layer formed of a compound semiconductor including In and Al, provided over the first semiconductor layer; source and drain electrodes provided on the second semiconductor layer; and a gate electrode provided between the source and drain electrodes, on the second semiconductor layer. The compound semiconductor in the second semiconductor layer has a first In composition ratio in a region on a side facing the substrate and a second In composition ratio in a region on an opposite side, the second In composition ratio being lower than the first In composition ratio, and the source and drain electrodes are provided in contact with the region having the first In composition ratio, and the gate electrode is provided on the region having the second In composition ratio.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: The teachings of the present disclosure relate to electrical circuits and embodiments may include a circuit arrangement and a current converter comprising said circuit arrangement. An example circuit arrangement may include: a carrier part; a power component; a cooling channel for conveying a cooling agent; and a busbar conducting a current to the power component. The busbar may be arranged on the carrier part and have a region with a first surface and a second surface arranged opposite the first surface. The region may project away from the carrier part into the cooling channel. The power component may be arranged on the first surface of the region and connected to the region in an electrically conductive and mechanical manner.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer.

Abstract: In an embodiment, the film product includes a film substrate having a first surface and a second surface opposite the first surface. The film substrate has a length in a first direction and a width in a second direction perpendicular to the first direction. A first plurality of pads is on one of the first surface and the second surface, and the first plurality of pads is arranged in a third direction, the third direction being diagonal with respect to at least one of the first direction and the second direction. At least one merge line is electrically connecting at least two of the first plurality of pads.

Abstract: The present invention provides a micro LED array substrate encapsulation structure and an encapsulation method thereof. The micro LED array substrate encapsulation structure of the present invention includes a base plate, a micro LED array, and a photoresist protection layer. The micro LED array includes a plurality of micro LEDs arranged in an array. The photoresist protection layer is formed with a plurality of vias at locations corresponding to the plurality of micro LEDs. The plurality of micro LEDs are respectively located in the plurality of vias. Each of the vias is filled therein with a UV resin microlens that has an upper surface in a bulging form and covers the micro LED in the corresponding one of the vias. The micro LEDs and driving substrates located thereunder can be protected and an effect of light emission of the micro LED array substrate can be improved.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor having a substrate, a first electrode layer on the substrate, a first dielectric layer on the first electrode layer where the first dielectric layer has a columnar-oriented grain structure, a group of second dielectric layers stacked on the first dielectric layer where each of the group of second dielectric layers has a randomly-oriented grain structure, and a second electrode layer on the group of second dielectric layers. Other embodiments are disclosed.

Abstract: Provided is a technique for forming a film having a desired stress on a substrate. A method of manufacturing a semiconductor device includes: forming a film having a predetermined stress on a substrate by controlling a ratio of a thickness of a first film having compressive stress to a thickness of a second film having tensile stress by performing: (a) supplying an organic source gas containing a first element and a reactive gas containing a second element to the substrate to form the first film containing the first element and the second element; and (b) supplying an inorganic source gas containing the first element and the reactive gas to the substrate to form the second film containing the first element and the second element.

Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.

Abstract: This invention relates to an EMI shielding composition comprising a thermoplastic resin and/or a thermoset resin, a solvent or a reactive diluent and conductive particles providing uniform and homogenous thickness to the EMI shielding layer. The invention also provides a process of applying the EMI shielding layer on the encapsulant protecting the CI device components.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.