Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.

Abstract: A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.

Abstract: A substrate structure for a micro electro mechanical system (MEMS) device, a semiconductor structure and a method for fabricating the same are provided. In various embodiments, the substrate structure for the MEMS device includes a substrate, the MEMS device, and an anti-stiction layer. The MEMS device is over the substrate. The anti-stiction layer is on a surface of the MEMS device, and includes amorphous carbon, polytetrafluoroethene, hafnium oxide, tantalum oxide, zirconium oxide, or a combination thereof.

Abstract: Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.

Abstract: The light-emitting device of the present invention includes: a support; a plurality of light-emitting elements arranged in a row on the support; and a conductor trace portion configured from a plurality of conductor traces which extend on the support from one end portion of the row to the other end portion of the row which are each electrically connected to each of the plurality of light-emitting elements. Each of the plurality of conductor traces is configured such that the trace width in the direction of extension in a region under one light-emitting element to which the conductor trace is electrically connected is greater than the trace width in a region extending in the direction of extension side by side with a conductor trace connected to a light-emitting element disposed closer to the one end portion than the one light-emitting element is.

Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.

Abstract: In a metrology sampling method with a sampling rate decision scheme, a mean absolute percentage error (MAPE) and a maximum absolute percentage error (MaxErr) of visual metrology values of all workpieces in a set of determinative samples (DS), and various index values that can detect various status changes of a process tool (such as maintenance operation, parts changing, parameter adjustment, etc.), and/or information abnormalities of the process tool (such as abnormal process data, parameter drift/shift, abnormal metrology data, etc.) appearing in a manufacturing process are applied to develop an automated sampling decision (ASD) scheme for reducing a workpiece sampling rate while VM accuracy is still sustained.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: A method for forming a semiconductor device includes forming a first insulator layer on a first substrate of a first semiconductor material, implanting hydrogen ions into the first substrate to form a hydrogen-implanted layer, forming a recessed region in the first substrate, forming a second semiconductor material in the recessed region, and forming a second insulator layer over the second semiconductor material and the first substrate. The method also includes providing a second substrate with a third insulator layer disposed thereon, bonding the first substrate with the second substrate, and removing a lower portion of the first substrate at the hydrogen-implanted layer. A portion of the first substrate is removed to expose a surface of the second semiconductor material in the recessed region, thereby providing a layer of the first semiconductor material adjacent to a layer of the second semiconductor material on the second insulator layer.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: A display panel, a display method thereof, and a manufacturing method thereof are provided. The display panel includes a plurality of sub-pixel units. Each of the sub-pixel units includes a first display area and a second display area; the first display area includes an active emitting display unit; and the second display area is configured to switch between a transparent state and an opaque state.

Abstract: Disclosed are process control systems and methods incorporating a crystal microbalance (CM) (e.g., a quartz crystal microbalance (QCM)) into gas flow line(s) entering and/or exiting a processing chamber. A CM measures the resonance of a quartz crystal sensor contained therein as gas flows over that crystal sensor and can, thereby be used to accurately monitor, in real time, the mass flow rate of the gas. The mass flow rate may indicate that gas contamination has occurred and, in response, a controller can cause the gas flow to stop. Additionally, the mass flow rate may indicate the desired result will not be achieved within the processing chamber and, in response, advanced process control (APC) can be performed (e.g., the controller can adjust the gas flow). CM(s) incorporated into gas flow lines entering and/or exiting a processing chamber can provide precise measurements for process monitoring at minimal cost.

Abstract: A high-brightness light-emitting diode with surface microstructure and preparation and screening methods thereof are provided. The ratio of total roughened surface area of light transmission surface of a light emitting diode to vertically projected area is greater than 1.5, and the peak density of light transmission surface is not less than 0.3/um2. The higher the ratio of total roughened surface area of an epitaxial wafer to vertically projected area and the higher the number of peak over the critical height within a unit area, the more beneficial to improve light extraction efficiency of the epitaxial wafer. As a result, light extraction efficiency of the epitaxial wafer is greatly improved.

Abstract: A light-emitting device and a method of manufacturing a light-emitting device are provided. The light-emitting device includes a transparent substrate having a first surface and a second surface opposite to the first surface, a light-emitting structure disposed on the first surface of the transparent substrate, a sealing layer, a carrier board, and a positive electrode and a negative electrode. The transparent substrate, the light-emitting structure, the sealing layer and the carrier board have corresponding through holes respectively, and at least one of the positive electrode and the negative electrode is disposed on the second surface of the transparent substrate.

Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.

Abstract: The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

Abstract: Methods for manufacturing a flexible display device are provided. A flexible substrate is provided and a first bonding pattern, which encloses a display area, is formed on the flexible substrate. A second bonding pattern is formed on a rigid substrate. The first and second bonding patterns are bonded together to provide a bonding pattern between the flexible substrate and the rigid substrate. At least one display device is formed on the display area of the flexible substrate. The bonding pattern is removed by a cutting process performed so as to separate the flexible substrate having the display device thereon from the rigid substrate.

Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.

Abstract: An optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component are disclosed. In an embodiment, the component includes a carrier, a multi-pixel semiconductor chip that emits electromagnetic radiation during operation, wherein the semiconductor chip is arranged on the carrier, and wherein the semiconductor chip has a plurality of individually activatable pixels capable of generating primary radiation and a wavelength conversion element for at least partially converting the primary radiation emitted from the semiconductor chip into electromagnetic secondary radiation, wherein an active zone of the multi-pixel semiconductor chip extends continuously over the plurality of pixels, and wherein the wavelength conversion element is implemented in one piece.

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.